Renesas M32R/ECU Series

(3)
6.4.2 Flash Status Registers ---------------------------------------------------------------------------------------- 6-5
6.4.3 Flash Status Register 2 (FSTAT2) ------------------------------------------------------------------------- 6-5
6.4.4 Flash Control Registers ---------------------------------------------------------------------------------------6-7
6.4.5 Virtual Flash S Bank Registers ----------------------------------------------------------------------------- 6-11
6.5 Programming the Internal Flash Memory----------------------------------------------------------------------------6-12
6.5.1 Outline of Internal Flash Memory Programming --------------------------------------------------------6-12
6.5.2 Controlling Operation Modes during Flash Programming --------------------------------------------6-17
6.5.3 P8 Data Register -----------------------------------------------------------------------------------------------6-18
6.5.4 Procedure for Programming/Erasing the Internal Flash Memory-----------------------------------6-20
6.5.5 Flash Programming Time (Reference) -------------------------------------------------------------------- 6-29
6.6 Virtual Flash Emulation Function -------------------------------------------------------------------------------------- 6-30
6.6.1 Virtual Flash Emulation Area --------------------------------------------------------------------------------6-31
6.6.2 Entering Virtual Flash Emulation Mode -------------------------------------------------------------------6-33
6.6.3 Application Example of Virtual Flash Emulation Mode ------------------------------------------------6-34
6.7 Connecting to A Serial Programmer ----------------------------------------------------------------------------------6-36
6.8 Internal Flash Memory Protect Function -----------------------------------------------------------------------------6-38
6.9 Precautions To Be Taken when Rewriting the Internal Flash Memory --------------------------------------6-39
CHAPTER 7 RESET
7.1 Outline of Reset ------------------------------------------------------------------------------------------------------------7-2
7.2 Reset Operation -----------------------------------------------------------------------------------------------------------7-2
7.2.1 Reset at Power-on ---------------------------------------------------------------------------------------------7-3
7.2.2 Reset during Operation ---------------------------------------------------------------------------------------7-3
7.2.3 Reset at Entering RAM Backup Mode --------------------------------------------------------------------7-3
7.2.4 Reset Vector Relocation during Flash Programming--------------------------------------------------7-3
7.3 Internal State Immediately after Reset -------------------------------------------------------------------------------7-4
7.4 Things to Be Considered after Reset ---------------------------------------------------------------------------------7-4
CHAPTER 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8.1 Outline of Input/Output Ports -------------------------------------------------------------------------------------------8-2
8.2 Selecting Pin Functions --------------------------------------------------------------------------------------------------8-3
8.3 Input/Output Port Related Registers ----------------------------------------------------------------------------------8-5
8.3.1 Port Data Registers -------------------------------------------------------------------------------------------- 8-7
8.3.2 Port Direction Registers --------------------------------------------------------------------------------------8-8
8.3.3 Port Operation Mode Registers ----------------------------------------------------------------------------- 8-9
8.3.4 Port Peripheral Output Select Registers------------------------------------------------------------------8-20
8.3.5 Port Input Special Function Control Register------------------------------------------------------------8-21
8.4 Port Input Level Switching Function ----------------------------------------------------------------------------------8-24
8.5 Port Peripheral Circuits --------------------------------------------------------------------------------------------------8-27
8.6 Precautions on Input/Output Ports ------------------------------------------------------------------------------------ 8-31
CHAPTER 9 DMAC
9.1 Outline of the DMAC ------------------------------------------------------------------------------------------------------ 9-2
9.2 DMAC Related Registers ------------------------------------------------------------------------------------------------9-4
9.2.1 DMA Channel Control Registers ---------------------------------------------------------------------------9-6
9.2.2 DMA Software Request Generation Registers----------------------------------------------------------9-18
9.2.3 DMA Source Address Registers ----------------------------------------------------------------------------9-19