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Renesas M32R/ECU Series User Manual
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Appendix 2
Appendix
2-4
32180 Group User's Manual (Rev. 1.0)
INSTRUCTION PROCESSING TIME
Appendix 2.1 32180 Instruction Processing Time
This page is blank for reasons of layout.
800
802
Table of Contents
Default Chapter
4
Revision History
4
Before Use
5
Table of Contents
6
Chapter 1 Overview
18
Outline of the 32180 Group
18
M32R Family CPU Core with Built-In FPU (M32R-FPU)
19
Built-In Multiplier/Accumulator
20
Built-In Single-Precision FPU
20
Built-In Flash Memory and RAM
20
Built-In Clock Frequency Multiplier
21
Powerful Peripheral Functions Built-In
21
Block Diagram
22
Pin Functions
25
Pin Assignments
31
Chapter 2 Cpu
38
CPU Registers
38
General-Purpose Registers
38
Control Registers
38
Processor Status Word Register: PSW (CR0)
40
Condition Bit Register: CBR (CR1)
41
Interrupt Stack Pointer: SPI (CR2) and User Stack Pointer: SPU (CR3)
41
Backup PC: BPC (CR6)
41
Floating-Point Status Register: FPSR (CR7)
42
Accumulator
44
Program Counter
44
Data Formats
45
Data Types
45
Supplementary Explanation for BSET, BCLR, LOCK and UNLOCK Instruction Execution
51
Precautions on CPU
51
Chapter 3 Address Space
52
Outline of the Address Space
52
Operation Modes
56
Internal ROM and Extended External Areas
56
Internal ROM Area
56
Extended External Area
56
Internal RAM and SFR Areas
57
Internal RAM Area
57
SFR (Special Function Register) Area
57
EIT Vector Entry
86
ICU Vector Table
87
Notes on Address Space
89
Chapter 4 Eit
90
Outline of EIT
90
EIT Events
92
Exception
92
Interrupt
94
Trap
95
EIT Processing Procedure
95
EIT Processing Mechanism
96
Acceptance of EIT Events
97
Saving and Restoring the PC and PSW
97
Exception Processing
100
Reserved Instruction Exception (RIE)
100
Address Exception (AE)
101
Floating-Point Exception (FPE)
102
Interrupt Processing
104
Reset Interrupt (RI)
104
System Break Interrupt (SBI)
104
External Interrupt (EI)
106
Trap Processing
107
Trap
107
EIT Priority Levels
108
Example of EIT Processing
109
Precautions on EIT
111
Chapter 5 Interrupt Controller (Icu)
112
Outline of the Interrupt Controller
112
ICU Related Registers
112
Interrupt Vector Register
116
Interrupt Request Mask Register
117
SBI (System Break Interrupt) Control Register
118
Interrupt Control Registers
119
Interrupt Request Sources in Internal Peripheral I/O
122
ICU Vector Table
123
Description of Interrupt Operation
124
Acceptance of Internal Peripheral I/O Interrupts
124
Processing by Internal Peripheral I/O Interrupt Handlers
126
Description of System Break Interrupt (SBI) Operation
129
Acceptance of SBI
129
SBI Processing by Handler
129
Chapter 6 Internal Memory
130
Outline of the Internal Memory
130
Internal RAM
130
Internal Flash Memory
131
Registers Associated with the Internal Flash Memory
133
Flash Mode Register
133
Flash Status Registers
134
Flash Status Register 2 (FSTAT2)
134
Flash Control Registers
136
Virtual Flash S Bank Registers
140
Programming the Internal Flash Memory
141
Outline of Internal Flash Memory Programming
141
Controlling Operation Modes During Flash Programming
146
P8 Data Register
147
Procedure for Programming/Erasing the Internal Flash Memory
149
Flash Programming Time (Reference)
158
Virtual Flash Emulation Function
159
Virtual Flash Emulation Area
160
Entering Virtual Flash Emulation Mode
162
Application Example of Virtual Flash Emulation Mode
163
Connecting to a Serial Programmer
165
Internal Flash Memory Protect Function
167
Precautions to be Taken When Rewriting the Internal Flash Memory
168
Chapter 7 Reset
170
Outline of Reset
170
Reset Operation
170
Reset at Power-On
172
Reset During Operation
172
Reset at Entering RAM Backup Mode
172
Reset Vector Relocation During Flash Programming
172
Internal State Immediately after Reset
173
Things to be Considered after Reset
173
Chapter 8 Input/Output Ports and Pin Functions
174
Outline of Input/Output Ports
174
Selecting Pin Functions
174
Input/Output Port Related Registers
174
Port Data Registers
180
Port Direction Registers
181
Port Operation Mode Registers
182
Port Peripheral Output Select Registers
193
Port Input Special Function Control Register
194
Port Input Level Switching Function
197
Port Peripheral Circuits
200
Precautions on Input/Output Ports
204
Chapter 9 Dmac
206
Outline of the DMAC
206
DMAC Related Registers
206
DMA Channel Control Registers
211
DMA Software Request Generation Registers
223
DMA Source Address Registers
224
DMA Destination Address Registers
225
DMA Transfer Count Registers
226
DMA Interrupt Related Registers
227
Functional Description of the DMAC
232
DMA Transfer Request Sources
232
DMA Transfer Processing Procedure
238
Starting DMA
239
DMA Channel Priority
239
Gaining and Releasing Control of the Internal Bus
239
Transfer Units
240
Transfer Counts
240
Address Space
240
Transfer Operation
240
End of DMA and Interrupt
242
Each Register Status after Completion of DMA Transfer
242
Precautions about the DMAC
243
Chapter 10 Multijunction Timers
244
Outline of Multijunction Timers
244
Common Units of Multijunction Timers
244
MJT Common Unit Register Map
253
Prescaler Unit
255
Clock Bus and Input/Output Event Bus Control Unit
256
Input Processing Control Unit
260
Output Flip-Flop Control Unit
269
Interrupt Control Unit
278
TOP (Output-Related 16-Bit Timer)
307
Outline of TOP
307
Outline of each Mode of TOP
309
TOP Related Register Map
311
TOP Control Registers
313
TOP Counters (TOP0CT-TOP10CT)
318
TOP Reload Registers (TOP0RL-TOP10RL)
319
TOP Correction Registers (TOP0CC-TOP10CC)
320
TOP Enable Control Registers
321
Operation in TOP Single-Shot Output Mode (with Correction Function)
323
Operation in TOP Delayed Single-Shot Output Mode (with Correction Function)
329
Operation in TOP Continuous Output Mode (Without Correction Function)
334
TIO (Input/Output-Related 16-Bit Timer)
337
Outline of TIO
337
Outline of each Mode of TIO
339
TIO Related Register Map
342
TIO Control Registers
344
TIO Counters (TIO0CT-TIO9CT)
352
TIO Reload 0/ Measure Registers (TIO0RL0-TIO9RL0)
353
TIO Reload 1 Registers (TIO0RL1-TIO9RL1)
354
TIO Enable Control Registers
355
Operation in TIO Measure Free-Run/ Clear Input Modes
357
Operation in TIO Noise Processing Input Mode
359
Operation in TIO PWM Output Mode
360
Operation in TIO Single-Shot Output Mode (Without Correction Function)
363
Operation in TIO Delayed Single-Shot Output Mode (Without Correction Function)
365
Operation in TIO Continuous Output Mode (Without Correction Function)
367
TMS (Input-Related 16-Bit Timer)
369
Outline of TMS
369
Outline of TMS Operation
369
TMS Related Register Map
371
TMS Control Registers
372
TMS Counters (TMS0CT, TMS1CT)
373
TMS Measure Registers (TMS0MR3-0, TMS1MR3-0)
373
Operation of TMS Measure Input
374
TML (Input-Related 32-Bit Timer)
375
Outline of TML
375
Outline of TML Operation
376
TML Related Register Map
376
TML Control Registers
377
TML Counters
378
TML Measure Registers
378
Operation of TML Measure Input
379
TID (Input-Related 16-Bit Timer)
381
Outline of TID
381
TID Related Register Map
383
TID Control & Prescaler Enable Registers
384
TID Counters (TID0CT, TID1CT and TID2CT)
387
TID Reload Registers (TID0RL, TID0RL and TID2RL)
387
Outline of each Mode of TID
388
TOU (Output-Related 24-Bit Timer)
393
Outline of TOU
393
Outline of each Mode of TOU
395
TOU Related Register Map
397
TOU Control Registers
401
TOU Counters
404
TOU Reload Registers
407
TOU Enable Protect Registers
411
TOU Count Enable Registers
412
PWMOFF Input Processing Control Registers
414
PWM Output Control Registers
417
PWM Output Disable Level Control Registers
420
Operation in TOU PWM Output Mode
422
Operation in TOU Single-Shot PWM Output Mode (Without Correction Function)
427
Operation in TOU Delayed Single-Shot Output Mode (Without Correction Function)
429
Operation in TOU Single-Shot Output Mode (Without Correction Function)
431
Operation in TOU Continuous Output Mode (Without Correction Function)
433
0% or 100% Duty-Cycle Wave Output During PWM Output and Single-Shot PWM Output Modes
435
PWM Output Disable Function
440
Example Application for Using the 32180 in Motor Control
444
Chapter 11 A-D Converters
446
Outline of A-D Converters
446
Conversion Modes
451
Operation Modes
451
Special Operation Modes
454
A-D Converter Interrupt and DMA Transfer Requests
457
Sample-And-Hold Function
457
A-D Converter Related Registers
458
A-D Single Mode Registers
461
A-D Single Mode Registers
463
A-D Scan Mode Registers
465
A-D Scan Mode Registers
467
A-D Conversion Speed Control Registers
469
A-D Disconnection Detection Assist Function Control Registers
470
A-D Disconnection Detection Assist Method Select Registers
471
A-D Successive Approximation Registers
474
A-D Comparate Data Registers
475
10-Bit A-D Data Registers
476
8-Bit A-D Data Registers
477
Functional Description of A-D Converters
478
How to Find Analog Input Voltages
478
A-D Conversion by Successive Approximation Method
479
Comparator Operation
480
Calculating the A-D Conversion Time
481
Accuracy of A-D Conversion
484
Inflow Current Bypass Circuit
486
Precautions on Using A-D Converters
488
Chapter 12 Serial I/O
492
Outline of Serial I/O
492
Serial I/O Related Registers
492
SIO Interrupt Related Registers
497
SIO Transmit Control Registers
505
SIO Transmit/Receive Mode Registers
506
SIO Transmit Buffer Registers
509
SIO Receive Buffer Registers
510
SIO Receive Control Registers
511
SIO Baud Rate Registers
514
Transmit Operation in CSIO Mode
515
Setting the CSIO Baud Rate
515
Initializing CSIO Transmission
516
Starting CSIO Transmission
518
Successive CSIO Transmission
518
Processing at End of CSIO Transmission
519
Transmit Interrupts
519
Transmit DMA Transfer Request
519
Example of CSIO Transmit Operation
521
Receive Operation in CSIO Mode
523
Initialization for CSIO Reception
523
Starting CSIO Reception
525
Processing at End of CSIO Reception
525
About Successive Reception
526
Flags Showing the Status of CSIO Receive Operation
527
Example of CSIO Receive Operation
528
Precautions on Using CSIO Mode
530
Transmit Operation in UART Mode
531
Setting the UART Baud Rate
531
UART Transmit/Receive Data Formats
531
Initializing UART Transmission
533
Starting UART Transmission
535
Successive UART Transmission
535
Processing at End of UART Transmission
535
Transmit Interrupts
535
Transmit DMA Transfer Request
536
Example of UART Transmit Operation
537
Receive Operation in UART Mode
539
Initialization for UART Reception
539
Starting UART Reception
541
Processing at End of UART Reception
541
Example of UART Receive Operation
543
Start Bit Detection During UART Reception
545
Fixed Period Clock Output Function
546
Precautions on Using UART Mode
547
Chapter 13 Can Module
548
Outline of the CAN Module
548
CAN Module Related Registers
548
CAN Control Registers
562
CAN Status Registers
565
CAN Frame Format Select Registers
568
CAN Configuration Registers
569
CAN Timestamp Count Registers
571
CAN Error Count Registers
572
CAN Baud Rate Prescalers
573
CAN Interrupt Related Registers
574
CAN Cause of Error Registers
592
CAN Mode Registers
593
CAN DMA Transfer Request Select Registers
594
CAN Mask Registers
595
CAN Single-Shot Mode Control Registers
599
CAN Message Slot Control Registers
600
CAN Message Slots
604
CAN Protocol
619
CAN Protocol Frames
619
Data Formats During CAN Transmission/Reception
620
CAN Controller Error States
621
Initializing the CAN Module
622
Transmitting Data Frames
625
Data Frame Transmit Procedure
625
Data Frame Transmit Operation
626
Transmit Abort Function
627
Receiving Data Frames
628
Data Frame Receive Procedure
628
Data Frame Receive Operation
629
Reading out Received Data Frames
631
Transmitting Remote Frames
633
Remote Frame Transmit Procedure
633
Remote Frame Transmit Operation
634
Reading out Received Data Frames When Set for Remote Frame Transmission
636
Receiving Remote Frames
638
Remote Frame Receive Procedure
638
Remote Frame Receive Operation
639
Precautions about CAN Module
642
Chapter 14 Real Time Debugger (Rtd)
644
Outline of the Real-Time Debugger (RTD)
644
Pin Functions of the RTD
644
Functional Description of the RTD
644
Outline of the RTD Operation
647
Operation of RDR (Real-Time RAM Content Output)
647
Operation of the WRR (RAM Content Forcible Rewrite)
649
Operation of VER (Continuous Monitor)
650
Operation of VEI (Interrupt Request)
650
Operation of RCV (Recover from Runaway)
651
Method for Setting a Specified Address When Using the RTD
652
Resetting the RTD
653
Typical Connection with the Host
654
Chapter 15 External Bus Interface
656
Outline of the External Bus Interface
656
External Bus Interface Related Signals
657
External Bus Interface Related Registers
659
Port Operation Mode Registers
659
Port Peripheral Output Select Register
663
Bus Mode Control Register
664
Read/Write Operations
665
Bus Arbitration
671
Typical Connection of External Extension Memory
673
Example of Bus Voltage Settings Using VCC-BUS
676
Chapter 16 Wait Controller
678
Outline of the Wait Controller
678
Wait Controller Related Registers
678
CS Area Wait Control Registers
681
Typical Operation of the Wait Controller
683
Chapter 17 Ram Backup Mode
704
Outline of RAM Backup Mode
704
Example of RAM Backup When Power Is down
704
Normal Operating State
706
RAM Backup State
707
Example of RAM Backup for Saving Power Consumption
708
Normal Operating State
708
RAM Backup State
709
Precautions to be Observed at Power-On
710
Exiting RAM Backup Mode (Wakeup)
711
Chapter 18 Oscillator Circuit
712
Oscillator Circuit
712
Example of an Oscillator Circuit
713
XIN Oscillation Stoppage Detection Circuit
714
Oscillation Drive Capability Select Function
716
System Clock Output Function
718
Oscillation Stabilization Time at Power-On
718
Clock Generator Circuit
719
Chapter 19 Jtag
720
Outline of JTAG
720
Configuration of the JTAG Circuit
720
JTAG Registers
723
Instruction Register (JTAGIR)
723
Data Register
724
Basic Operation of JTAG
725
Outline of JTAG Operation
725
IR Path Sequence
727
DR Path Sequence
728
Inspecting and Setting Data Registers
729
Boundary Scan Description Language
730
Notes on Board Design When Connecting JTAG
731
Processing Pins When Not Using JTAG
733
Chapter 20 Power Supply Circuit
734
Configuration of the Power Supply Circuit
734
Power-On Sequence
734
Power-On Sequence When Not Using RAM Backup
736
Power-On Sequence When Using RAM Backup
737
Power-Off Sequence
738
Power-Off Sequence When Not Using RAM Backup
738
Power-Off Sequence When Using RAM Backup
739
Chapter 21 Electrical Characteristics
742
Absolute Maximum Ratings
742
Electrical Characteristics When VCCE = 5 V, F(XIN) = 10 Mhz
744
Recommended Operating Conditions (When VCCE = 5 V, F(XIN) = 10 Mhz)
744
Characteristics (When VCCE = 5 V, F(XIN) = 10 Mhz)
746
A-D Conversion Characteristics (When VCCE = 5 V, F(XIN) = 10 Mhz)
747
Electrical Characteristics When VCCE = 5 V, F(XIN) = 8 Mhz
748
Recommended Operating Conditions (When VCCE = 5 V, F(XIN) = 8 Mhz)
748
Characteristics (When VCCE = 5 V, F(XIN) = 8 Mhz)
750
A-D Conversion Characteristics (When VCCE = 5 V, F(XIN) = 8 Mhz)
751
Electrical Characteristics When VCCE = 3.3 V, F(XIN) = 10 Mhz
752
Recommended Operating Conditions (When VCCE = 3.3 V ± 0.3 V, F(XIN) = 10 Mhz)
752
Characteristics (When VCCE = 3.3 V ± 0.3 V, F(XIN) = 10 Mhz)
754
A-D Conversion Characteristics (When VCCE = 3.3 V ± 0.3 V, F(XIN) = 10 Mhz)
755
Electrical Characteristics When VCCE = 3.3 V, F(XIN) = 8 Mhz
756
Recommended Operating Conditions (When VCCE = 3.3 V ± 0.3 V F(XIN) = 8 Mhz)
756
Characteristics (When VCCE = 3.3 V ± 0.3 V, F(XIN) = 8 Mhz)
758
A-D Conversion Characteristics (When VCCE = 3.3 V ± 0.3 V, F(XIN) = 8 Mhz)
759
Flash Memory Related Characteristics
760
Characteristics (When VCCE = 5 V)
761
Timing Requirements
761
Switching Characteristics
765
Characteristics
765
Characteristics (When VCCE = 3.3 V)
768
Timing Requirements
777
Switching Characteristics
781
Characteristics
781
Chapter 22 Typical Characteristics
794
To be Written at a Later Time
795
Appendix 1 Mechanical Specificaitons
796
Appendix 1.1 Dimensional Outline Drawing
796
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Renesas M32R/ECU Series Specifications
General
Brand
Renesas
Model
M32R/ECU Series
Category
Computer Hardware
Language
English
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