Allen-Bradley SLC 500 - Page 187

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• Siemens QUICKDESIGNER
Tag Name Address Bit Write Value Example PLC Name Notes
Range Range Range
I 000-127
(1)
0 - 7(req) NO 0 - 1 I00.5 PL, IPB
IB 000-127
(1)
N/S NO 0 - 255 IB12 IB012
IW 000-126
(1)
N/S NO 0-65535 IW0 IW000 Input word
(3)
Q 000-127
(1)
0 - 7(req) NO 0 - 1 Q00.6 None
QB 000-127
(1)
N/S NO 0 - 255 QB26 QB026
QW 000-126
(1)
N/S NO 0-65535 QW0 QW000 Output word
(3)
F 000-255
(1)
0 - 7(req) YES 0 - 1 F00.2 None
FY 000-255
(1)
N/S YES 0 - 255 FY45 FY045
FW 000-255
(1)
N/S YES 0-65535 FW0 FW0 Flag word
(3)
T 000-255
(1)
N/S YES 0-999 T0 T0 Timer
(4)
C 000-255
(1)
N/S YES 0-999 C0 C0 Counter
(4)
ASC 1-999 YES ASCII Double
D 000-255
(1,2)
00-15(opt) YES -32768 to D01000 DB010:DW000
32767 D01000.7 NONE Default memory
(5)
DB#:DL# 000-255
(1)
N/S NO 0 - 255 DB04:L8 DB004:DL008 Byte format (8 bits).
DB#:DR# 000-255
(1)
N/S NO 0 - 255 DB05:L7 DB005:DL007 Byte format (8 bits).
DB#:DW# 006-255
(1,6)
00-15(opt) YES -32768 to DB012:10 DB012:DW010 Word format (16
bits).
32767 DB011:13.7 NONE Bit writes are RMW
DB#:DD# 000 - 255 YES -100000000 to
100000000 Double
DB#:DF# 000 - 255 YES -99999999 to
99999999 Float
I Input
IW Input Word
Q Output
QW Output Word
FFlags
FW Flag Word
TTimer Word
C Counter Word
D Data Word
Note 1: The maximum address is determined by the processor type and memory configuration.
Note 2: Both the address and data block range.
Note 3: Double byte memory (8 + 8 bits, B1 & B0), only even addresses are supported.
Note 4: Word memory, typically BCD format.
Note 5: Default memory type, word Bit writes are RMW
Note 6: Lowest block is DB06
(req) = required, (opt) = optional