5
5-3
INTERRUPT CONTROLLER (ICU)
32180 Group User’s Manual (Rev.1.0)
Interrupt Vector Register
(IVECT)
Interrupt Request Mask
Register (IMASK)
NEW_IMASK
External Interrupt (EI)
request generated
(maskable)
IMASK
compari-
son
ILEVEL
System Break Interrupt (SBI)
request generated
(nonmaskable)
SBI#
EI
SBI
Interrupt Controller
Interrupt Control Register
SBI Control Register
(SBICR)
SBIREQ
IREQ
IREQ
IREQ
IREQ
IREQ
IREQ
Peripheral circuits
Edge
Interrupt
control circuit
Edge
Edge
Level
Interrupt request
Interrupt request
Interrupt request
Level
Level
To the CPU core
To the CPU core
Interrupt
control circuit
Interrupt
control circuit
Priority resolved by interrupt priority levels set
Priority resolved by fixed hardware priority
Figure 5.1.1 Block Diagram of the Interrupt Controller
5.1 Outline of the Interrupt Controller