9
9-10
DMAC
32180 Group User’s Manual (Rev.1.0)
DMA4 Channel Control Register 0 (DM4CNT0)
<Address: H
’0080 0450>123456b7b0
SADSL4 DADSL4MDSEL4 TREQF4 REQSL4 TENL4 TSZSL4
00000000
<After reset: H’00>
b Bit Name Function R W
0 MDSEL4 0: Normal mode R W
DMA4 transfer mode select bit 1: Ring buffer mode
1 TREQF4 0: Transfer not requested R(Note 1)
DMA4 transfer request flag bit 1: Transfer requested
2, 3 REQSL4 00: Software start R W
DMA4 transfer request source select bit 01: One DMA3 transfer completed
10: SIO0_RXD
11: Extended DMA4 transfer request source select
(DMA4 Channel Control Register 1)
4 TENL4 0: Disable transfer R W
DMA4 transfer enable bit 1: Enable transfer
5 TSZSL4 0: 16 bits R W
DMA4 transfer size select bit 1: 8 bits
6 SADSL4 0: Fixed R W
DMA4 source address direction select bit 1: Increment
7 DADSL4 0: Fixed R W
DMA4 destination address direction select bit 1: Increment
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
DMA4 Channel Control Register 1 (DM4CNT1)
<Address: H
’0080 0451>9 10 11 12 13 14 b15b8
REQESEL4
0000
<After reset: H’00>
b Bit Name Function R W
8–11 No function assigned. Fix to "0". 00
12–15 REQESEL4 0000: MJT(TIN19S) R W
Extended DMA4 transfer request source select bit 0001: SIO0_TXD (transmit buffer empty)
0010: MJT(TOU1_7irq)
0011: Common 1) MJT (input event bus 1)
0100: Common 2) MJT (input event bus 3)
0101: Common 3) MJT (output event bus 2)
0110: Common 4) MJT (output event bus 3)
0111: Common 5) AD0 conversion completed
1000: Common 6) MJT (TIN0S)
1001: Common 7) MJT (TIO8_udf)
1010: Settings inhibited
1111: Settings inhibited
9.2 DMAC Related Registers
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