Renesas M32R/ECU Series - Page 216

9
DMAC
9-11
32180 Group User’s Manual (Rev.1.0)
DMA5 Channel Control Register 0 (DM5CNT0) <Address: H’0080 0418>
123456b7b0
SADSL5 DADSL5MDSEL5 TREQF5
REQSL5
TENL5 TSZSL5
00000000
<After reset: H’00>
b Bit Name Function R W
0 MDSEL5 0: Normal mode R W
DMA5 transfer mode select bit 1: Ring buffer mode
1 TREQF5 0: Transfer not requested R(Note 1)
DMA5 transfer request flag bit 1: Transfer requested
2, 3 REQSL5 00: Software start or one DMA7 transfer completed R W
DMA5 transfer request source select bit 01: All DMA0 transfers completed
10: SIO2_RXD
11: Extended DMA5 transfer request source select
(DMA5 Channel Control Register 1)
4 TENL5 0: Disable transfer R W
DMA5 transfer enable bit 1: Enable transfer
5 TSZSL5 0: 16 bits R W
DMA5 transfer size select bit 1: 8 bits
6 SADSL5 0: Fixed R W
DMA5 source address direction select bit 1: Increment
7 DADSL5 0: Fixed R W
DMA5 destination address direction select bit 1: Increment
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
DMA5 Channel Control Register 1 (DM5CNT1) <Address: H’0080 0419>
9 10 11 12 13 14 b15b8
REQESEL5
0000
0
0
0
0
<After reset: H’00>
b Bit Name Function R W
8–11 No function assigned. Fix to "0". 00
12–15 REQESEL5 0000: MJT(TIN20S) R W
Extended DMA5 transfer request source select bit 0001: MJT(TOU0_0irq)
0010: MJT(TOU2_7irq)
0011: Common 1) MJT (input event bus 1)
0100: Common 2) MJT (input event bus 3)
0101: Common 3) MJT (output event bus 2)
0110: Common 4) MJT (output event bus 3)
0111: Common 5) AD0 conversion completed
1000: Common 6) MJT (TIN0S)
1001: Common 7) MJT (TIO8_udf)
1010: Settings inhibited
1111: Settings inhibited
9.2 DMAC Related Registers
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