9
9-12
DMAC
32180 Group User’s Manual (Rev.1.0)
DMA6 Channel Control Register 0 (DM6CNT0)
<Address: H
’0080 0428>123456b7b0
SADSL6 DADSL6MDSEL6 TREQF6
REQSL6
TENL6 TSZSL6
00000000
<After reset: H’00>
b Bit Name Function R W
0 MDSEL6 0: Normal mode R W
DMA6 transfer mode select bit 1: Ring buffer mode
1 TREQF6 0: Transfer not requested R(Note 1)
DMA6 transfer request flag bit 1: Transfer requested
2, 3 REQSL6 00: Software start R W
DMA6 transfer request source select bit 01: SIO1_TXD (transmit buffer empty)
10: MJT(TIN1S)
11: Extended DMA6 transfer request source select
(DMA6 Channel Control Register 1)
4 TENL6 0: Disable transfer R W
DMA6 transfer enable bit 1: Enable transfer
5 TSZSL6 0: 16 bits R W
DMA6 transfer size select bit 1: 8 bits
6 SADSL6 0: Fixed R W
DMA6 source address direction select bit 1: Increment
7 DADSL6 0: Fixed R W
DMA6 destination address direction select bit 1: Increment
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
DMA6 Channel Control Register 1 (DM6CNT1)
<Address: H
’0080 0429>9 10 11 12 13 14 b15b8
REQESEL6
0000
<After reset: H’00>
b Bit Name Function R W
8–11 No function assigned. Fix to "0". 00
12–15 REQESEL6 0000: One DMA5 transfer completed R W
Extended DMA6 transfer request source select bit 0001: MJT(TOU0_1irq)
0010: SIO1_RXD
0011: Common 1) MJT (input event bus 1)
0100: Common 2) MJT (input event bus 3)
0101: Common 3) MJT (output event bus 2)
0110: Common 4) MJT (output event bus 3)
0111: Common 5) AD0 conversion completed
1000: Common 6) MJT (TIN0S)
1001: Common 7) MJT (TIO8_udf)
1010: Settings inhibited
1111: Settings inhibited
9.2 DMAC Related Registers
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