9
9-14
DMAC
32180 Group User’s Manual (Rev.1.0)
DMA8 Channel Control Register 0 (DM8CNT0)
<Address: H
’0080 0448>123456b7b0
SADSL8 DADSL8MDSEL8 TREQF8 REQSL8 TENL8 TSZSL8
00000000
<After reset: H’00>
b Bit Name Function R W
0 MDSEL8 0: Normal mode R W
DMA8 transfer mode select bit 1: Ring buffer mode
1 TREQF8 0: Transfer not requested R(Note 1)
DMA8 transfer request flag bit 1: Transfer requested
2, 3 REQSL8 00: Software start R W
DMA8 transfer request source select bit 01: MJT (input event bus 0)
10: SIO3_RXD
11: Extended DMA8 transfer request source select
(DMA8 Channel Control Register 1)
4 TENL8 0: Disable transfer R W
DMA8 transfer enable bit 1: Enable transfer
5 TSZSL8 0: 16 bits R W
DMA8 transfer size select bit 1: 8 bits
6 SADSL8 0: Fixed R W
DMA8 source address direction select bit 1: Increment
7 DADSL8 0: Fixed R W
DMA8 destination address direction select bit 1: Increment
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
DMA8 Channel Control Register 1 (DM8CNT1)
<Address: H
’0080 0449>9 10 11 12 13 14 b15b8
REQESEL8
0000
<After reset: H’00>
b Bit Name Function R W
8–11 No function assigned. Fix to "0". 00
12–15 REQESEL8 0000: MJT(TIN7S) R W
Extended DMA8 transfer request source select bit 0001: MJT(TOU0_6irq)
0010: One DMA7 transfer completed
0011: Common 1) MJT (input event bus 1)
0100: Common 2) MJT (input event bus 3)
0101: Common 3) MJT (output event bus 2)
0110: Common 4) MJT (output event bus 3)
0111: Common 5) AD0 conversion completed
1000: Common 6) MJT (TIN0S)
1001: Common 7) MJT (TIO8_udf)
1010: Settings inhibited
1111: Settings inhibited
9.2 DMAC Related Registers
| |
To Next Page
Loading...
Need help?
General
