9
9-28
DMAC
32180 Group User’s Manual (Rev.1.0)
Table 9.3.2 DMA Transfer Request Sources and Generation Timings on DMA1
REQSL1 DMA Transfer Request Source DMA Transfer Request Generation Timing
0 0 Software start When any data is written to the DMA1 Software Request Generation Register
0 1 MJT (output event bus 0) When MJT output event bus 0 signal is generated
1 0 MJT (TIN13 input signal) When MJT TIN13 input signal is generated
1 1 Extended DMA1 transfer request The source selected by the DMA1 Channel Control Register 1 (DM1CNT1)
source selected REQESEL1 bits (see below)
REQESEL1 DMA Transfer Request Source DMA Transfer Request Generation Timing
0000 One DMA0 transfer completed When one DMA0 transfer is completed (cascade mode)
0001 MJT (TIN3 input signal) When MJT TIN3 input signal is generated
0010 MJT (TID1_udf/ovf) When MJT TID1 underflow/overflow occurs
0011 MJT (input event bus 1) When MJT input event bus 1 signal is generated
0100 MJT (input event bus 3) When MJT input event bus 3 signal is generated
0101 MJT (output event bus 2) When MJT output event bus 2 signal is generated
0110 MJT (output event bus 3) When MJT output event bus 3 signal is generated
0111 A-D0 conversion completed When A-D0 conversion is completed
1000 MJT (TIN0 input signal) When MJT TIN0 input signal is generated
1001 MJT (TIO8_udf) When MJT TIO8 underflow occurs
1010
| Settings inhibited –
1111
Table 9.3.3 DMA Transfer Request Sources and Generation Timings on DMA2
REQSL2 DMA Transfer Request Source DMA Transfer Request Generation Timing
0 0 Software start When any data is written to the DMA2 Software Request Generation Register
0 1 MJT (output event bus 1) When MJT output event bus 1 signal is generated
1 0 MJT (TIN18 input signal) When MJT TIN18 input signal is generated
1 1 Extended DMA2 transfer request The source selected by the DMA2 Channel Control Register 1 (DM2CNT1)
source selected REQESEL2 bits (see below)
REQESEL2 DMA Transfer Request Source DMA Transfer Request Generation Timing
0000 One DMA0 transfer completed When one DMA0 transfer is completed (cascade mode)
0001 MJT(TID2_udf/ovf) When MJT TID2 underflow/overflow occurs
0010 CAN(CAN0_S1/S14) When CAN0 slot 1 transmission failed or slot 14 transmission reception finished
0011 MJT (input event bus 1) When MJT input event bus 1 signal is generated
0100 MJT (input event bus 3) When MJT input event bus 3 signal is generated
0101 MJT (output event bus 2) When MJT output event bus 2 signal is generated
0110 MJT (output event bus 3) When MJT output event bus 3 signal is generated
0111 A-D0 conversion completed When A-D0 conversion is completed
1000 MJT (TIN0 input signal) When MJT TIN0 input signal is generated
1001 MJT (TIO8_udf) When MJT TIO8 underflow occurs
1010
| Settings inhibited –
1111
9.3 Functional Description of the DMAC
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