9
9-32
DMAC
32180 Group User’s Manual (Rev.1.0)
Table 9.3.10 DMA Transfer Request Sources and Generation Timings on DMA9
REQSL9 DMA Transfer Request Source DMA Transfer Request Generation Timing
0 0 Software start When any data is written to the DMA9 Software Request Generation Register
0 1 Serial I/O3 (transmit buffer empty) When serial I/O3 transmit buffer is empty
1 0 MJT (TIN8 input signal) When MJT TIN8 input signal is generated
1 1 Extended DMA9 transfer request The source selected by the DMA9 Channel Control Register 1 (DM9CNT1)
source selected REQESEL9 bits (see below)
REQESEL9 DMA Transfer Request Source DMA Transfer Request Generation Timing
0000 One DMA8 transfer completed When one DMA8 transfer is completed (cascade mode)
0001 MJT (TOU0_7irq) MJT TOU0_7 interrupt source
0010 A-D0 conversion completed When A-D0 conversion is completed
0011 MJT (input event bus 1) When MJT input event bus 1 signal is generated
0100 MJT (input event bus 3) When MJT input event bus 3 signal is generated
0101 MJT (output event bus 2) When MJT output event bus 2 signal is generated
0110 MJT (output event bus 3) When MJT output event bus 3 signal is generated
0111 A-D0 conversion completed When A-D0 conversion is completed
1000 MJT (TIN0 input signal) When MJT TIN0 input signal is generated
1001 MJT (TIO8_udf) When MJT TIO8 underflow occurs
1010
| Settings inhibited –
1111
9.3 Functional Description of the DMAC
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