To Next Page

To Previous Page

10-15

MULTIJUNCTION TIMERS

10.2 Common Units of Multijunction Timers

32180 Group User’s Manual (Rev.1.0)

Figure 10.2.1 Conceptual Diagram of the Clock Bus and Input/Output Event Bus

Clock bus Input event bus

TCLK0S

3 2 1 0

TCLK0 (P124)

TIN0 (P150)

TIN2 (P152)

TIN3 (P153)

TIN4 (P154)

TIN5 (P155)

TIN6 (P156)

PRS1

PRS0

PRS0–2

: Prescaler

3 2 1 0

3 2 1 0 3 2 1 0

PRS2

TCLK3 (P127)

udf

TIO 5

udf

TIO 6

Output event bus

0 1 2 3

udf

TIO 7

clk

udf

TOP 6

clk

udf

TOP 7

clk

udf

TOP 8

clk

udf

TOP 9

udf

TIO 0

udf

TIO 1

udf

TIO 2

udf

TIO 3

udf

TIO 4

udf

TIO 8

0 1 2 3

: Selector

TCLK3S

TIN0S

TIN2S

TIN3S

TIN4S

TIN5S

TIN6S

BCLK/2

Default Chapter4
- Revision History4
- Before Use5
- Table of Contents6
Chapter 1 Overview18
- Outline of the 32180 Group18
- Block Diagram22
- Pin Functions25
- Pin Assignments31
Chapter 2 Cpu38
- CPU Registers38
- General-Purpose Registers38
- Control Registers38
- Accumulator44
- Program Counter44
- Data Formats45
  - Data Types45
- Supplementary Explanation for BSET, BCLR, LOCK and UNLOCK Instruction Execution51
- Precautions on CPU51
Chapter 3 Address Space52
- Outline of the Address Space52
- Operation Modes56
- Internal ROM and Extended External Areas56
  - Internal ROM Area56
  - Extended External Area56
- Internal RAM and SFR Areas57
  - Internal RAM Area57
  - SFR (Special Function Register) Area57
- EIT Vector Entry86
- ICU Vector Table87
- Notes on Address Space89
Chapter 4 Eit90
- Outline of EIT90
- EIT Events92
- EIT Processing Procedure95
- EIT Processing Mechanism96
- Acceptance of EIT Events97
- Saving and Restoring the PC and PSW97
- Exception Processing100
- Interrupt Processing104
- Trap Processing107
  - Trap107
- EIT Priority Levels108
- Example of EIT Processing109
- Precautions on EIT111
Chapter 5 Interrupt Controller (Icu)112
- Outline of the Interrupt Controller112
- ICU Related Registers112
- Interrupt Request Sources in Internal Peripheral I/O122
- ICU Vector Table123
- Description of Interrupt Operation124
  - Acceptance of Internal Peripheral I/O Interrupts124
  - Processing by Internal Peripheral I/O Interrupt Handlers126
- Description of System Break Interrupt (SBI) Operation129
  - Acceptance of SBI129
  - SBI Processing by Handler129
Chapter 6 Internal Memory130
- Outline of the Internal Memory130
- Internal RAM130
- Internal Flash Memory131
- Registers Associated with the Internal Flash Memory133
- Programming the Internal Flash Memory141
- Virtual Flash Emulation Function159
- Connecting to a Serial Programmer165
- Internal Flash Memory Protect Function167
- Precautions to be Taken When Rewriting the Internal Flash Memory168
Chapter 7 Reset170
- Outline of Reset170
- Reset Operation170
- Internal State Immediately after Reset173
- Things to be Considered after Reset173
Chapter 8 Input/Output Ports and Pin Functions174
- Outline of Input/Output Ports174
- Selecting Pin Functions174
- Input/Output Port Related Registers174
- Port Input Level Switching Function197
- Port Peripheral Circuits200
- Precautions on Input/Output Ports204
Chapter 9 Dmac206
- Outline of the DMAC206
- DMAC Related Registers206
- Functional Description of the DMAC232
- Precautions about the DMAC243
Chapter 10 Multijunction Timers244
- Outline of Multijunction Timers244
- Common Units of Multijunction Timers244
- TOP (Output-Related 16-Bit Timer)307
- TIO (Input/Output-Related 16-Bit Timer)337
- TMS (Input-Related 16-Bit Timer)369
- TML (Input-Related 32-Bit Timer)375
- TID (Input-Related 16-Bit Timer)381
- TOU (Output-Related 24-Bit Timer)393
Chapter 11 A-D Converters446
- Outline of A-D Converters446
- A-D Converter Related Registers458
- Functional Description of A-D Converters478
- Inflow Current Bypass Circuit486
- Precautions on Using A-D Converters488
Chapter 12 Serial I/O492
- Outline of Serial I/O492
- Serial I/O Related Registers492
- Transmit Operation in CSIO Mode515
- Receive Operation in CSIO Mode523
- Precautions on Using CSIO Mode530
- Transmit Operation in UART Mode531
- Receive Operation in UART Mode539
- Fixed Period Clock Output Function546
- Precautions on Using UART Mode547
Chapter 13 Can Module548
- Outline of the CAN Module548
- CAN Module Related Registers548
- CAN Protocol619
- Initializing the CAN Module622
- Transmitting Data Frames625
- Receiving Data Frames628
- Transmitting Remote Frames633
- Receiving Remote Frames638
  - Remote Frame Receive Procedure638
  - Remote Frame Receive Operation639
- Precautions about CAN Module642
Chapter 14 Real Time Debugger (Rtd)644
- Outline of the Real-Time Debugger (RTD)644
- Pin Functions of the RTD644
- Functional Description of the RTD644
- Typical Connection with the Host654
Chapter 15 External Bus Interface656
- Outline of the External Bus Interface656
  - External Bus Interface Related Signals657
- External Bus Interface Related Registers659
- Read/Write Operations665
- Bus Arbitration671
- Typical Connection of External Extension Memory673
- Example of Bus Voltage Settings Using VCC-BUS676
Chapter 16 Wait Controller678
- Outline of the Wait Controller678
- Wait Controller Related Registers678
  - CS Area Wait Control Registers681
- Typical Operation of the Wait Controller683
Chapter 17 Ram Backup Mode704
- Outline of RAM Backup Mode704
- Example of RAM Backup When Power Is down704
  - Normal Operating State706
  - RAM Backup State707
- Example of RAM Backup for Saving Power Consumption708
- Exiting RAM Backup Mode (Wakeup)711
Chapter 18 Oscillator Circuit712
- Oscillator Circuit712
- Clock Generator Circuit719
Chapter 19 Jtag720
- Outline of JTAG720
- Configuration of the JTAG Circuit720
- JTAG Registers723
  - Instruction Register (JTAGIR)723
  - Data Register724
- Basic Operation of JTAG725
- Boundary Scan Description Language730
- Notes on Board Design When Connecting JTAG731
- Processing Pins When Not Using JTAG733
Chapter 20 Power Supply Circuit734
- Configuration of the Power Supply Circuit734
- Power-On Sequence734
  - Power-On Sequence When Not Using RAM Backup736
  - Power-On Sequence When Using RAM Backup737
- Power-Off Sequence738
  - Power-Off Sequence When Not Using RAM Backup738
  - Power-Off Sequence When Using RAM Backup739
Chapter 21 Electrical Characteristics742
- Absolute Maximum Ratings742
- Electrical Characteristics When VCCE = 5 V, F(XIN) = 10 Mhz744
- Electrical Characteristics When VCCE = 5 V, F(XIN) = 8 Mhz748
- Electrical Characteristics When VCCE = 3.3 V, F(XIN) = 10 Mhz752
- Electrical Characteristics When VCCE = 3.3 V, F(XIN) = 8 Mhz756
- Flash Memory Related Characteristics760
- Characteristics (When VCCE = 5 V)761
- Characteristics (When VCCE = 3.3 V)768
Chapter 22 Typical Characteristics794
- To be Written at a Later Time795
Appendix 1 Mechanical Specificaitons796
Appendix 1.1 Dimensional Outline Drawing796

Brand	Renesas
Model	M32R/ECU Series
Category	Computer Hardware
Language	English

Renesas M32R/ECU Series User Manual

Table of Contents

Questions and Answers:

Renesas M32R/ECU Series Specifications

Related product manuals