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10.4 TIO (Input/Output-Related 16-Bit Timer)
MULTIJUNCTION TIMERS
32180 Group User’s Manual (Rev.1.0)
(4) Single-shot output mode (without correction function)
In single-shot output mode, the timer generates a pulse in width of (reload 0 register set value + 1) only once
and then stops.
When the timer is enabled (by writing to the enable bit in software or by external input) after setting the reload
0 register, the counter is loaded with the reload 0 register value and starts counting synchronously with the
count clock. The counter counts down and when the minimum count is reached, stops upon underflow.
The F/F output waveform in single-shot output mode is inverted at startup and upon underflow, generating a
single-shot pulse waveform in width of (reload 0 register set value + 1) only once. An interrupt request can be
generated when the counter underflows.
(5) Delayed single-shot output mode (without correction function)
In delayed single-shot output mode, the timer generates a pulse in width of (reload 0 register set value + 1)
after a finite time equal to (counter set value + 1) only once and then stops.
When the timer is enabled (by writing to the enable bit in software or by external input) after setting the
counter and reload 0 register, it starts counting down from the counter’s set value synchronously with the
count clock. The first time the counter underflows, it is loaded with the reload 0 register value and continues
counting down. The counter stops when it underflows next time.
The F/F output waveform in delayed single-shot output mode is inverted when the counter underflows first
time and next, generating a single-shot pulse waveform in width of (reload 0 register set value + 1) after a
finite time equal to (first set value of counter + 1) only once. An interrupt request can be generated when the
counter underflows first time and next.
(6) Continuous output mode (without correction function)
In continuous output mode, the timer counts down starting from the set value of the counter and when the
counter underflows, it is loaded with the reload 0 register value. Thereafter, this operation is repeated each
time the counter underflows, thus generating consecutive pulses in width of (reload 0 register set value + 1).
When the timer is enabled (by writing to the enable bit in software or by external input) after setting the
counter and reload 0 register, it starts counting down from the counter’s set value synchronously with the
count clock and when the minimum count is reached, generates an underflow. This underflow causes the
counter to be loaded with the content of the reload 0 register and start counting over again. Thereafter, this
operation is repeated each time an underflow occurs. To stop the counter, disable count by writing to the
enable bit in software.
The F/F output waveform in continuous output mode is inverted at startup and upon underflow, generating a
waveform of consecutive pulses until the timer stops counting. An interrupt request can be generated each
time the counter underflows.
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