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MULTIJUNCTION TIMERS
10.8 TOU (Output-Related 24-Bit Timer)
32180 Group User’s Manual (Rev.1.0)
Figure 10.8.17 Typical Operation in PWM Output Mode (Reload 0 Register: H’FFFF)
Note 1: DMA transfer request also is generated with the same timing.
Note: • This diagram does not show detailed timing information.
• This diagram is shown with respect to the one-count-clock delayed output.
Enabled
(by writing to the enable bit or by
external input)
Count down from
the reload 1
register set value
Count down from
the reload 1
register set value
Underflow
Superficial
underflow
H'FFFF
H'0000
H'FFFF
H'E000
H'(E000-1)
H'(FFFF-1)H'(FFFF-1)
H'(E000-1)
H'E000
Data not invertedData not inverted Data not inverted
Counter
Because the reload 0 register = H'FFFF,
a superficial underflow is generated,
causing the counter to be loaded with
the content of the reload 1 register
Undefined
value
Enable bit
Reload 0 register
Reload 1 register
F/F output
Interrupt request
due to underflow
(Note 1)
Timing at which startup requests to other timers are generated
Count clock
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