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Renesas M32R/ECU Series

Renesas M32R/ECU Series
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10
10-194
MULTIJUNCTION TIMERS
10.8 TOU (Output-Related 24-Bit Timer)
32180 Group Users Manual (Rev.1.0)
Figure 10.8.18 Typical Operation in PWM Output Mode (Reload 1 Register: H’FFFF)
Enabled
(by writing to the enable bit
or by external input)
H'FFFF
H'0000
H'E000
H'E000
H'(E000-1)
H'(FFFF-1) H'(FFFF-1)
H'(E000-1)
H'FFFF
Data inverted by enable
Note 1: DMA transfer request also is generated with the same timing.
Note:This diagram does not show detailed timing information.
Data not inverted
Counter
Undefined
value
Enable bit
Reload 0 register
Reload 1 register
F/F output
Interrupt request
due to underflow
(Note 1)
Timing at which startup requests to other timers are generated
Count clock
Data not inverted
Count down from
the reload 0
register set value
Underflow
Superficial
underflow
Because the reload 1 register = H'FFFF,
a superficial underflow is generated,
causing the counter to be loaded with
the content of the reload 0 register
Count down from
the reload 0
register set value

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