15
15-12
EXTERNAL BUS INTERFACE
32180 Group User’s Manual (Rev.1.0)
Figure 15.3.3 Read/Write Timing (for Access with Internal 2 and External 1 Wait States)
Read
Write
Read (4 cycles)
BCLK
A11–A30
CS0#–CS3#
BHW#, BLW#
DB0–DB15
WAIT#
RD#
"H"
Note 1: For details about the Bus Mode Control Register, see Section 15.2.3, "Bus Mode Control Register."
Note 2: For details about the CS Area Wait Control Register, see Section 16.2.1, "CS Area Wait Control Registers."
Note: • Circles in the above diagram denote the sampling timing.
"L"
Internal
2 wait states
External
1 wait state
(Don't Care)
"H"
(Don't Care)
Write (4 cycles)
BCLK
A11–A30
CS0#–CS3#
BHW#, BLW#
DB0–DB15
WAIT#
RD#
"H"
"L"
(Don't Care)
"H"
(Don't Care)
Bus Mode Control Register (Note 1)
BUSMOD bit = 0 (WR signal separated)
CS Area Wait Control Register (Note 2)
WTCSEL bit = 010 (2 wait)
SWAIT bit = 0 (without strobe wait)
RECOV bit = 0 (without recovery cycle)
IDLE bit = 0 (without idle cycle)
Internal
2 wait states
External
1 wait state
15.3 Read/Write Operations
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