15
15-14
EXTERNAL BUS INTERFACE
32180 Group User’s Manual (Rev.1.0)
Figure 15.3.5 Read/Write Timing (for Zero Wait Access)
Read
Write
BCLK
A11–A30
CS0#–CS3#
BHE#, BLE#
DB0–DB15
WAIT#
RD#
"H"
Note 1: For details about the Bus Mode Control Register, see Section 15.2.3, "Bus Mode Control Register."
Note 2: For details about the CS Area Wait Control Register, see Section 16.2.1, "CS Area Wait Control Registers."
Notes: • When zero wait state is selected, assertion of WAIT# is not accepted.
• BCLK is not output.
Read (1 cycle)
WR#
(Don't Care)
BCLK
A11–A30
CS0#–CS3#
BHE#, BLE#
DB0–DB15
WAIT#
RD#
"H"
Write (1 cycle)
WR#
(Don't Care)
Bus Mode Control Register (Note 1)
BUSMOD bit = 1 (byte enable separated)
CS Area Wait Control Register (Note 2)
WTCSEL bit = 000 (zero wait)
SWAIT bit = 0 (without strobe wait)
RECOV bit = 0 (without recovery cycle)
IDLE bit = 0 (without idle cycle)
15.3 Read/Write Operations
To Next Page
Loading...
