Appendix 4
Appendix 4-6
32180 Group User's Manual (Rev. 1.0)
SUMMARY OF PRECAUTIONS
Appendix 4.8 Precautions about the Multijunction Timers
Appendix 4.8.1 Precautions on Using TOP Single-Shot Output Mode
The following describes precautions to be observed when using TOP single-shot output mode.
• If the counter stops due to an underflow in the same clock period as the timer is enabled by external input,
the former has priority so that the counter stops.
• If the counter stops due to an underflow in the same clock period as count is enabled by writing to the enable
bit, the latter has priority so that count is enabled.
• If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable
bit, the latter has priority so that count is disabled.
• Because the timer operates synchronously with the count clock, a count clock-dependent delay is included
before F/F output is inverted after the timer is enabled.
• When writing to the correction register, be careful not to cause the counter to overflow. Even if the counter
overflows due to correction of counts, no interrupt requests are generated for reasons of an overflow. There-
fore, if the counter underflows in the subsequent down-count after an overflow, a false interrupt request is
generated for an underflow that includes the overflowed count.
In the example in the next page, the reload register is initially set to H’FFF8. When the timer starts, the reload
register value is loaded into the counter, letting it start counting down. In the example here, the value H’0014 is
written to the correction register when the counter has counted down to H’FFF0.
As a result of this correction, the count overflows to H’0004 and the counter fails to count correctly. Also, an
interrupt request is generated for an erroneous overflowed count.
Appendix 4.8 Precautions about the Multijunction Timers
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