Instrument Functions
R&S
®
FSVA/FSV
461Operating Manual 1176.7510.02 ─ 09
If a power sensor is selected as the trigger mode, the following softkeys are not availa-
ble; these settings are configured in the "Power Sensor Configuration" dialog box (see
Chapter 3.9.5, "Power Sensor Configuration Dialog", on page 547).
●
Trg/Gate Level
●
Trg/Gate Polarity
●
Trigger Hysteresis
●
Trigger Holdoff
Note: For R&S power sensors, the "Gate Mode" Lvl is not supported. The signal sent
by these sensors merely reflects the instant the level is first exceeded, rather than a
time period. However, only time periods can be used for gating in level mode. Thus,
the trigger impulse from the sensors is not long enough for a fully gated measurement;
the measurement cannot be completed.
Remote command:
TRIG:SOUR PSE, see TRIGger<n>[:SEQuence]:SOURce on page 909
SWE:EGAT:SOUR PSE for gated triggering, see [SENSe:]SWEep:EGATe:SOURce
on page 854
TRACe<n>:IQ:SET on page 901
Time ← Trg/Gate Source
Opens an edit dialog box to define a repetition interval in which the measurement is
triggered. The shortest interval is 2 ms.
Remote command:
TRIG:SOUR TIMETRIGger<n>[:SEQuence]:SOURce on page 909
Digital IQ ← Trg/Gate Source
For I/Q Analyzer or AnalogDemod mode only:
Defines triggering of the measurement directly via the LVDS connector. In the sub-
menu you must specify which general purpose bit (GP0 to GP5) will provide the trigger
data.
This trigger mode is available for input from the R&S Digital I/Q Interface (option
R&S FSV-B17) only.
A Trigger Offset, and Trg/Gate Polarity can be defined for the Digital IQ trigger to
improve the trigger stability, but no hysteresis or holdoff value.
The following table describes the assignment of the general purpose bits to the LVDS
connector pins.
(See Table 3-21)
Table 3-11: Assignment of general purpose bits to LVDS connector pins
Bit LVDS pin
GP0 SDATA4_P - Trigger1
GP1 SDATA4_P - Trigger2
GP2 SDATA0_P - Reserve1
GP3 SDATA4_P - Reserve2
Instrument Functions - I/Q Analyzer
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