Note: DCLS is DC Level Shifted output, pulse width modulated with
a position identifier having a positive pulse width equal to 0.8 of the
reciprocal of the bit rate, a binary one (1) having a positive pulse
width equal to 0.5 of the reciprocal of the bit rate and a binary zero
(0) having a positive pulse width equal to 0.2 of the reciprocal of the
bite rate.
VersaSync can provide various IRIG code in amplitude modulated (AM) or pulse
width coded (TTL) formats, depending on your unit configuration and additional
options. A signature control feature may be enabled for any IRIG output. Sig-
nature control removes the modulation code when a Time Sync Alarm is asser-
ted.
5.4.3 IRIG B Output
The IRIG B Time Code description follows.
Figure 5-1: IRIG B time code description
VersaSync User Manual 377
APPENDIX
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