Intel Cyclone 10 GX User Manual

Acronym Definition
MAC Media Access Control.
MII Media independent interface.
OSI Open System Interconnection.
PCS Physical Coding Sublayer.
PHY Physical Layer in OSI 7-layer architecture, also in Intel device scope is: PCS + PMA.
PMA Physical Medium Attachment.
PMD Physical Medium Dependent.
SGMII Serial Gigabit Media Independent Interface.
WAN Wide Area Network.
XAUI 10 Gigabit Attachment Unit Interface.
2.7. PCI Express (PIPE)
You can use Cyclone 10 GX transceivers to implement a complete PCI Express solution
for Gen1 and Gen2 at data rates of 2.5 and 5.0 Gbps, respectively.
Configure the transceivers for PCIe functionality using one of the following methods:
• Cyclone 10 GX Hard IP for PCIe
This is a complete PCIe solution that includes the Transaction, Data Link, and
PHY/MAC layers. The Hard IP solution contains dedicated hard logic, which
connects to the transceiver PHY interface.
• Native PHY IP Core in PIPE Gen1/Gen2 Transceiver Configuration Rules
Use the Native PHY IP Core to configure the transceivers in PCIe mode, giving
access to the PIPE interface (commonly called PIPE mode in transceivers). This
mode enables you to connect the transceiver to a third-party MAC to create a
complete PCIe solution.
The PIPE specification (version 2.0) provides implementation details for a PCIe-
compliant physical layer. The Native PHY IP Core for PIPE Gen1 and Gen2 supports
x1, x2 or x4 operation for a total aggregate bandwidth ranging from 2 to 16 Gbps.
In a x1 configuration, the PCS and PMA blocks of each channel are clocked and
reset independently. The x2 and x4 configurations support channel bonding for
two-lane and four-lane links. In these bonded channel configurations, the PCS and
PMA blocks of all bonded channels share common clock and reset signals.
Gen1 and Gen2 modes use 8B/10B encoding, which has a 20% overhead to overall
link bandwidth. Gen1 and Gen2 modes use the Standard PCS, for its operation.
Table 117. Transceiver Solutions
Support Cyclone 10 GX Hard IP for PCI
Express
Native PHY IP Core for PCI Express
(PIPE)
Gen1 and Gen2 data rates Yes Yes
MAC, data link, and transaction layer Yes User implementation in FPGA fabric
Transceiver interface Hard IP through PIPE 2.0 based
interface
• PIPE 2.0 for Gen1 and Gen2
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English