Intel Cyclone 10 GX User Manual

• PIPE Design Example
For more information about the PLL configuration for PCIe.
• Transmit PLL recommendation based on Data rates on page 200
For more information about ATX PLL placement restrictions
2.7.4. How to Implement PCI Express (PIPE) in Cyclone 10 GX
Transceivers
You must be familiar with the Standard PCS architecture, PLL architecture, and the
reset controller before implementing the PCI Express protocol.
1. Go to the IP Catalog and select the Cyclone 10 GX Transceiver Native PHY IP
Core. Refer to Select and Instantiate the PHY IP Core on page 17 for more details.
2. Select Gen1/Gen2 PIPE from the Cyclone 10 GX Transceiver configuration
rules list, located under Datapath Options.
3. Use the parameter values in the tables in Transceiver Native PHY IP Parameters for
PCI Express Transceiver Configurations Rules as a starting point. Alternatively, you
can use Cyclone 10 GX Transceiver Native PHY Presets . You can then modify
the settings to meet your specific requirements.
4. Click Finish to generate the Native PHY IP (this is your RTL file).
5. Instantiate and configure your PLL.
6. Create a transceiver reset controller. You can use your own reset controller or use
the Transceiver PHY Reset Controller.
7. Connect the Native PHY IP to the PLL IP core and the reset controller. Use the
information in Transceiver Native PHY IP Ports for PCI Express Transceiver
Configuration Rules to connect the ports.
8. Simulate your design to verify its functionality.
2.7.5. Native PHY IP Parameter Settings for PIPE
Table 120. Parameters for Cyclone 10 GX Native PHY IP in PIPE Gen1, Gen2 Modes
This section contains the recommended parameter values for this protocol. Refer to Using the Cyclone 10 GX
Transceiver Native PHY IP Core for the full range of parameter values.
Gen1 PIPE
Gen2 PIPE
Parameter
Message level for rule violations Error Error
Common PMA Options
VCCR_GXB and VCCT_GXB supply voltage
for the Transceiver
Gen1: 0_9V Gen2: 0_9V
Transceiver link type Gen1: sr Gen2: sr
Datapath Options
Transceiver configuration rules Gen1 PIPE Gen2 PIPE
PMA configuration rules Basic Basic
Transceiver mode TX / RX Duplex TX / RX Duplex
Number of data channels Gen1 x1: 1 channel Gen2 x1: 1 channel
continued...
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English