Figure 26. RX FIFO Deskew
rx_enh_data_valid
rx_enh_fifo_rd_en
rx_enh_fifo_full
rx_enh_fifo_pfull
rx_enh_fifo_empty
rx_enh_fifo_pempty
rx_enh_fifo_align_val
rx_enh_frame_lock
rx_enh_fifo_align_clr
3f
00
00
00
00
3f
00
3f
3f
00
00
3f
[5]
[4]
[3]
[2]
[1]
[0]
00
21 3f
21 3f3b
1e
001e
Each Lane Is
Frame-Locked
in a Different
Cycle
After deskew is successful, the user
logic asserts rd_en for all lanes to start
reading data from the RX FIFO.
data_valid is asserted,
indicating that the RX FIFO
is outputting valid data.
Deassertion of pempty
of all lanes before any
lane pfull goes high,
which means the deskew
is complete.
2.5.3. How to Implement Interlaken in Cyclone 10 GX Transceivers
You should be familiar with the Interlaken protocol, Enhanced PCS and PMA
architecture, PLL architecture, and the reset controller before implementing the
Interlaken protocol PHY layer.
Cyclone 10 GX devices provide three preset variations for Interlaken in the IP
Parameter Editor:
• Interlaken 1x6.25 Gbps
• Interlaken 6x10.3 Gbps
1. Instantiate the Cyclone 10 GX Transceiver Native PHY IP from the IP Catalog
(Installed IP ➤ Library ➤ Interface Protocols ➤ Transceiver PHY ➤
Cyclone 10 GX Transceiver Native PHY).
Refer to Select and Instantiate the PHY IP Core on page 17 for more details.
2. Select Interlaken from the Transceiver configuration rules list located under
Datapath Options, depending on which protocol you are implementing.
3. Use the parameter values in the tables in Transceiver Native PHY IP Parameters for
Interlaken Transceiver Configuration Rules.... Or you can use the protocol presets
described in Transceiver Native PHY Presets. You can then modify the settings to
meet your specific requirements.
4. Click Generate to generate the Native PHY IP (this is your RTL file).
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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