Intel Cyclone 10 GX User Manual

To perform dynamic reconfiguration using direct reconfiguration flow:
1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Read from the desired feature address.
3. Perform a read-modify-write to feature address with a valid value.
4. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
Related Information
• Steps to Perform Dynamic Reconfiguration on page 328
• Changing PMA Analog Parameters on page 338
• Using Data Pattern Generators and Checkers on page 359
• Resetting Transceiver Channels on page 243
• Calibration on page 373
6.10. Native PHY IP or PLL IP Core Guided Reconfiguration Flow
Use the Native PHY IP core or PLL IP core guided reconfiguration flow to perform
dynamic reconfiguration when you need to change multiple parameters or parameters
in multiple addresses for the transceiver channel or PLL. You can use this flow to
change data rates, change clock divider values, or switch from one PCS datapath to
another. You must generate the required configuration files for the base and modified
Transceiver Native PHY IP core or PLL IP core configurations.
The configuration files contain addresses and bit values of the corresponding
configuration. Compare the differences between the base and modified configuration
files. The differences between these files indicate the addresses and bit values that
must change to switch from one configuration to another. Perform read-modify-writes
for the bit values that are different from the base configuration to obtain the modified
configuration.
To perform dynamic reconfiguration using the IP Guided Reconfiguration Flow:
1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Perform a read-modify-write to all addresses and bit values that are different from
the base configuration.
3. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
Note: If reconfiguration involved data rate or protocol mode changes, you may need to
reconfigure the PMA analog parameters of the channels. Refer to the Changing PMA
Analog Parameters section for more details.
The bit values that must be changed to obtain the new configuration may span across
multiple addresses, such as when switching between Standard, Enhanced, and PCS
Direct data paths. It is difficult to manually compare these values for the base and
modified configurations and then build logic to stream the different values in the
modified configuration. You can use the multiple profiles feature of the Native PHY/ATX
PLL IP cores to store the parameter settings (MIF configuration file) to memory. With
the configuration content saved, you can read from the memory and write the content
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English