Intel Cyclone 10 GX User Manual

Refer to Steps to Perform Dynamic Reconfiguration for a complete list of steps to
perform dynamic reconfiguration using the IP guided reconfiguration flow with multiple
reconfiguration profiles enabled.
The Quartus Prime Timing Analyzer Timing Analyzer will only include the necessary
PCS timing paths for all the profiles. To perform a PMA reconfiguration such as TX PLL
switching, CGB divider switching, or reference clock switching, you must use the flow
described in Steps to Perform Dynamic Reconfiguration. Refer to Timing Closure
Recommendations for more details about enabling multiple profiles and running timing
analyses.
You can use the multiple reconfiguration profiles feature without using the embedded
reconfiguration streamer feature. When using the multiple reconfiguration profiles
feature by itself, you must write the user logic to reconfigure all the entries that are
different between the profiles while moving from one profile to another.
Note: You must ensure that none of the profiles in the Native PHY IP and ATX PLL IP
Parameter Editor gives error messages, or the IP generation will fail. The Native PHY
IP core and ATX PLL IP only validates the current active profile dynamically. For
example, if you store a profile with error messages in the Native PHY IP or ATX PLL IP
Parameter Editor and load another profile without any error messages, the error
messages will disappear in the IP. You will then be allowed to generate the IP, but the
generation will fail.
Related Information
• Steps to Perform Dynamic Reconfiguration on page 328
• Timing Closure Recommendations on page 369
• Analog Parameter Settings on page 388
6.5. Embedded Reconfiguration Streamer
You can optionally enable the embedded reconfiguration streamer in the Native PHY
and/or ATX PLL IP cores to automate the reconfiguration operation. The embedded
reconfiguration streamer is a feature block that can perform Avalon-MM transactions
to access channel/ATX PLL configuration registers in the transceiver. When you enable
the embedded streamer, the Native PHY/ATX PLL IP cores will embed HDL code for
reconfiguration profile storage and reconfiguration control logic in the IP files.
For the ATX PLL IP, you can control the embedded streamer block through the
reconfiguration interface. Control and status signals of the streamer block are memory
mapped in the PLL’s soft control and status registers.
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-20070 | 2018.09.24
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English