Intel Cyclone 10 GX User Manual

2.2. Transceiver Design Flow
Figure 8. Transceiver Design Flow
Generate PHY IP Core
Connect Transceiver Datapath to MAC IP Core or to a Data Generator / Analyzer
Select PLL IP Core
Generate the Transceiver PHY Reset Controller
or create your own User-Coded Reset Controller
Compile Design
Verify Design Functionality
Generate PLL IP Core
Configure the PHY IP Core
Select PHY IP Core
Configure the PLL IP Core
Connect PHY IP Core to PLL IP Core, Reset Controller, and
connect reconfiguration logic via Avalon-MM interface
Create reconfiguration logic
(if needed)
Make analog parameter settings to I/O pins using the Assignment Editor or updating the Quartus Prime Settings File
2.2.1. Select and Instantiate the PHY IP Core
Select the appropriate PHY IP core to implement your protocol.
Refer to the Cyclone 10 GX Transceiver Protocols and PHY IP Support section to decide
which PHY IP to select to implement your protocol.
You can create your Quartus Prime project first, and then instantiate the various IPs
required for your design. In this case, specify the location to save your IP HDL files.
The current version of the PHY IP does not have the option to set the speed grade.
Specify the device family and speed grade when you create the Quartus Prime project.
You can also instantiate the PHY IP directly to evaluate the various features.
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English