Intel Cyclone 10 GX User Manual

Figure 72. Word Aligner in Deterministic Mode Waveform
rx_clkout
rx_std_wa_patternalign
rx_parallel_data
rx_errdetect
rx_disperr
rx_patterndetect
rx_syncstatus
f1e4b6e4
1101
1101
0000
0000
0000
0000
1010
1010
1000
1000
0010
0000
1010
1010
0000
0000
1111
1111
0000
b9dbf1db 915d061d e13f913f 7a4ae24a bbae9b10 bcbcbcbc 95cd3c50 91c295cd
Related Information
Word Aligner on page 305
2.8.2.1.1. Transmitter and Receiver Latency
The latency variation from the link synchronization function (in the word aligner block)
is deterministic with the rx_bitslipboundaryselectout port. Additionally, you
can use the tx_bitslipboundaryselect port to fix the round trip transceiver
latency for port implementation in the remote radio head to compensate for latency
variation in the word aligner block. The tx_bitslipboundaryselect port is
available to control the number of bits to be slipped in the transmitter serial data
stream. You can optionally use the tx_bitslipboundaryselect port to round the
round-trip latency to a whole number of cycles.
When using the byte deserializer, additional logic is required in the FPGA fabric to
determine if the comma byte is received in the lower or upper byte of the word. The
delay is dependent on the word in which the comma byte appears.
Note: Latency numbers are pending device characterization.
2.8.3. Word Aligner in Manual Mode for CPRI
When configuring the word aligner in CPRI (Manual), the word aligner parses the
incoming data stream for a specific alignment character. After rx_digitalreset
deasserts, asserting the rx_std_wa_patternalign triggers the word aligner to look
for the predefined word alignment pattern or its complement in the received data
stream. It is important to note that the behavior of the word aligner in Manual mode
operates in different ways depending on the PCS-PMA interface width.
Table 134. Word Aligner Signal Status Behaviors in Manual Mode
PCS-PMA Interface Width
rx_std_wa_patternalign
Behavior
rx_syncstatus Behavior rx_patterndetect
Behavior
10 Level sensitive One parallel clock cycle (When
three control patterns are
detected)
One parallel clock cycle
20 Edge sensitive Remains asserted until next
rising edge of
rx_std_wa_patternalign
One parallel clock cycle
PCS-PMA Width = 10
When the PCS-PMA interface width is 10, 3 consecutive word alignment patterns found
after the initial word alignment in a different word boundary causes the word aligner
to resynchronize to this new word boundary if the rx_std_wa_patternalign
remains asserted; rx_std_wa_patternalign is level sensitive. If you deassert
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English