Intel Cyclone 10 GX User Manual

2.3. Cyclone 10 GX Transceiver Protocols and PHY IP Support
Table 3. Cyclone 10 GX Transceiver Protocols and PHY IP Support
Protocol Transceiver PHY IP
Core
PCS Support Transceiver
Configuration Rule
Protocol Preset
PCIe Gen2 x1, x2, x4 Native PHY IP (PIPE)
core/Hard IP for PCI
Express
(1)
Standard Gen2 PIPE PCIe PIPE Gen2 x1
(2)
PCIe Gen1 x1, x2, x4 Native PHY IP (PIPE)
core/Hard IP for PCI
Express
(1)
Standard Gen1 PIPE User created
(3)
1000BASE-X Gigabit
Ethernet
Native PHY IP core Standard GbE GIGE - 1.25 Gbps
1000BASE-X Gigabit
Ethernet with 1588
Native PHY IP core Standard GbE 1588 GIGE - 1.25 Gbps
1588
10GBASE-R Native PHY IP core Enhanced 10GBASE-R 10GBASE-R Low
Latency
10GBASE-R 1588 Native PHY IP core Enhanced 10GBASE-R 1588 10GBASE-R
(4)
40GBASE-R Native PHY IP core Enhanced Basic (Enhanced PCS) Low Latency Enhanced
PCS
(5)
Interlaken (CEI-6G-SR
and CEI-11G-SR)
(6)
Native PHY IP core Enhanced Interlaken Interlaken
10x12.5Gbps
Interlaken
6x10.3Gbps
Interlaken
1x6.25Gbps
OTU-1 (2.7G) Native PHY IP core Standard Basic/Custom
(Standard PCS)
User created
continued...
(1)
Hard IP for PCI Express is also available as a separate IP core.
(2)
For x2 and x4 modes, select PCIe PIPE Gen2 x8. Then change the number of data channels
from 8 to 4.
(3)
For PCIe Gen1 x1 mode, select PCIe PIPE Gen2 x1 mode. Then change the transceiver
configuration rule from Gen 2 PIPE to Gen 1 PIPE.
For PCIe Gen1 x2 and x4 mode, select PCIe PIPE Gen2 x8. Then change the transceiver
configuration rule from Gen2 PIPE to Gen1 PIPE and number of data channels from 8 to 2 or 4.
(4)
Select the 10GBASE-R preset. Then change the transceiver configuration rule from 10GBASE-R
to 10GBASE-R 1588.
(5)
To implement 40GBASE-R using the Low Latency Enhanced PCS preset, change the number of
data channels to four and select appropriate PCS- FPGA Fabric and PCS-PMA width.
(6)
Link training, auto speed negotiation and sequencer functions are not included in the Native
PHY IP. The user would have to create soft logic to implement these functions when using
Native PHY IP.
A Transmit PCS soft bonding logic required for multi-lane bonding configuration is provided in
the design example.
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Intel
®
Cyclone
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English