Intel Cyclone 10 GX User Manual

In order to prevent the performance degradation, configure the devices as long as it is
powered up to normal operations. For idle transceiver RX channels, compile designs
with the assignment described in the link shown below. The CLKUSR pin must be
assigned a 100-125 MHz clock. For used transceiver TX and RX channels, do not
assert the analog reset signals indefinitely.
Related Information
Unused Transceiver channels Settings on page 402
For more information about unused or idle transceiver clock lines in the design. It
describes the unused or idle transceiver clock lines assignments in the qsf file.
3.9. Channel Bonding
For Cyclone 10 GX devices, two types of bonding modes are available:
• PMA bonding
• PMA and PCS bonding
Related Information
Resetting Transceiver Channels on page 243
Refer to the Timing Constraints for Bonded PCS and PMA Channels section in the
Resetting Transceiver Channels chapter for additional details.
3.9.1. PMA Bonding
PMA bonding reduces skew between PMA channels. In PMA bonding, only the PMA
portion of the transceiver datapath is skew compensated and the PCS is not skew
compensated.
In Cyclone 10 GX devices, there are two PMA bonding schemes:
• x6/xN bonding
• PLL feedback compensation bonding
In either case, the channels in the bonded group need not be placed contiguously.
3.9.1.1. x6/xN Bonding
In x6/xN bonding mode, a single transmit PLL is used to drive multiple channels.
3. PLLs and Clock Networks
UG-20070 | 2018.09.24
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English