Intel Cyclone 10 GX User Manual

Case Word Input Output
LW I-DS I-DS I-In
4 UW S I-In S
LW OS OS I-In
Figure 194. IDLE Word Insertion
This figure shows the insertion of IDLE words in the receiver data stream.
Idle Inserted
Before Insertion
After Insertion
FD000000000004AEh BBBBBB9CDDDDDD9Ch 0707070707070707h 00000000000000FBh
FD000000000004AEh BBBBBB9CDDDDDD9Ch 00000000000000FBh AAAAAAAAAAAAAAAAh
rx_parallel_data[79:0]
rx_parallel_data[79:0]
5.2.2.10.5. Basic Mode
In Basic mode, the RX FIFO operates as an elastic buffer, where buffer depths can
vary. This mode allows driving write and read side of RX FIFO with different clock
frequencies. Monitor the FIFO flag to control write and read operations. For RX FIFO,
assert rx_enh_read_en signal with rx_fifo_pfull signal going low.
5.3. Cyclone 10 GX Standard PCS Architecture
The standard PCS can operate at a data rate of up to 10.8 Gbps. Protocols such as
PCI-Express, CPRI 4.1, GigE, IEEE 1588 are supported in Hard PCS while the other
protocols can be implemented using Basic/Custom (Standard PCS) transceiver
configuration rules.
Figure 195. Standard PCS Datapath Diagram
RX
FIFO
Byte
Deserializer
8B/10B Decoder
Rate Match FIFO
Receiver PMA
Word Aligner
Deserializer
CDR
Receiver Standard PCS
Transmitter Standard PCS
Transmitter PMA
Serializer
tx_serial_data
rx_serial_data
FPGA
Fabric
TX
FIFO
Byte Serializer
8B/10B Encoder
PRBS
Generator
TX Bit Slip
/2, /4
/2, /4
Parallel Clock
Serial Clock
Parallel and Serial Clock
Parallel and Serial Clock
Clock Divider
rx_pma_div_clkout
Serial Clock
Clock Generation Block (CGB)
ATX PLL
CMU PLL
fPLL
tx_coreclkin
rx_coreclkin
rx_clkout or
tx_clkout
Parallel Clock
(Recovered)
Parallel Clock
(From Clock
Divider)
tx_clkout
tx_clkout
tx_clkout
rx_clkout
PRBS
Verifier
tx_pma_div_clkout
5. Cyclone 10 GX Transceiver PHY Architecture
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English