1. Intel
®
Cyclone
®
10 GX Transceiver PHY Overview
This user guide provides details about the Intel
®
Cyclone
®
10 GX transceiver physical
(PHY) layer architecture, PLLs, clock networks, and transceiver PHY IP core. Intel
Quartus
®
Prime Pro Edition software version 17.1 supports the Intel Cyclone 10 GX
transceiver PHY IP core. It also provides protocol specific implementation details and
describes features such as transceiver reset and dynamic reconfiguration of
transceiver channels and PLLs.
Intel’s FPGA Intel Cyclone 10 GX devices offer up to 12 transceiver channels with
integrated advanced high speed analog signal conditioning and clock data recovery
techniques.
The Intel Cyclone 10 GX devices have transceiver channels that can support data rates
up to 12.5 Gbps for chip-to-chip and chip-to-module communication, and up to 6.6
Gbps for backplane communication. You can achieve transmit and receive data rates
below 1.0 Gbps with oversampling.
UG-20070 | 2018.09.24
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and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
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