Intel Cyclone 10 GX User Manual

Figure 154. Dynamic Reconfiguration of Receiver Channel During Device Operation
1 3
Device Power Up
rx_cal_busy
rx_analogreset
rx_is_lockedtodata
rx_digitalreset
2 4 5
Legal
Reconfiguration
Window
t
req
t
LTD
min 4 μs
t
req
= 70 μs
4.3.2. Model 2: Acknowledgment Model
The acknowledgment model uses an event-driven mechanism. It is used for
applications with strict timing requirements. Instead of waiting for a minimum
assertion time of 70 μs for tx_analogreset and rx_analogreset, you must wait
to receive the acknowledgment from the Transceiver Native PHY IP core to ensure
successful assertion and deassertion of the analog resets.
To enable the acknowledgment model, enable the following ports in the Transceiver
Native PHY IP core:
•
Enable the tx_analog_reset_ack port in the TX PMA
Figure 155. Enabling the tx_analog_reset_ack Port
•
Enable the rx_analog_reset_ack port in the RX PMA
Figure 156. Enabling the rx_analog_reset_ack Port
4. Resetting Transceiver Channels
UG-20070 | 2018.09.24
Intel
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Cyclone
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English