Intel Cyclone 10 GX User Manual

Parameter Range
Enable PCIe pipe_hclk_in and pipe_hclk_out ports Off
Enable PCIe electrical idle control and status ports Off
Enable PCIe pipe_rx_polarity port Off
Table 151. Dynamic Reconfiguration Parameters
Parameter Range
Enable dynamic reconfiguration On/Off
Share reconfiguration interface On/Off
Enable Altera Debug Master Endpoint On/Off
Table 152. Generation Options Parameters
Parameter Range
Generate parameter documentation file On/Off
Related Information
Using the Cyclone 10 GX Transceiver Native PHY IP Core on page 26
2.9.3. How to Implement PCS Direct Transceiver Configuration Rule
You should be familiar with PCS Direct architecture, PMA architecture, PLL
architecture, and the reset controller before implementing PCS Direct Transceiver
Configuration Rule.
1. Open the IP Catalog and select Cyclone 10 GX Transceiver Native PHY IP.
2. Select PCS Direct from the Transceiver configuration rules list located under
Datapath Options.
3. Configure your Native PHY IP.
4. Click Generate to generate the Native PHY IP (this is your RTL file).
5. Instantiate and configure your PLL.
6. Create a transceiver reset controller. You can use your own controller or use the
Transceiver PHY Reset Controller.
7. Connect the Native PHY IP to the PLL IP and the reset controller.
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English