Intel Cyclone 10 GX User Manual

Figure 124. x1 Clock Lines
CMU or CDR
CGB
Ch 4
CDR
CGB
Ch 3
CDR
CGB
Ch 2
CGB
Ch 1
CDR
CGB
Ch 0
CDR
CGB
Ch 5
x1 Network
Master
CGB
Master
CGB
ATX PLL1
ATX PLL0
fPLL1
fPLL0
CMU or CDR
3.3.2. x6 Clock Lines
The x6 clock lines route the clock within a transceiver bank. The x6 clock lines are
driven by the master CGB. The master CGB can only be driven by the ATX PLL or the
fPLL. Because the CMU PLLs cannot drive the master CGB, the CMU PLLs cannot be
used for bonding purposes. There are two x6 clock lines per transceiver bank, one for
each master CGB. Any channel within a transceiver bank can be driven by the x6 clock
lines.
3. PLLs and Clock Networks
UG-20070 | 2018.09.24
Intel
®
Cyclone
®
10 GX Transceiver PHY User Guide
Send Feedback
212

Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English