Intel Cyclone 10 GX User Manual

4.2. Transceiver PHY Implementation
Figure 146. Typical Transceiver PHY Implementation
(user-coded
Reset Controller
Transceiver PHY Instance
tx_analogreset
tx_digitalreset
rx_analogreset
rx_digitalreset
tx_cal_busy (1)
rx_cal_busy
rx_is_lockedtoref
rx_is_lockedtodata
Transmit
PLL
pll_powerdown
pll_cal_busy (1)
pll_locked
clock
Receiver
PCS
Receiver
PMA
Transmitter
PCS
Transmitter
PMA
or Intel IP)
Notes:
(1) You can logical OR the pll_cal_busy and tx_cal_busy signals.
(2) tx_analogreset_ack and rx_analogreset_ack are status signals from the Transceiver PHY IP core when these ports are enabled for manual user implementation of Model 2.
tx_analogreset_ack (2)
rx_analogreset_ack (2)
reset_req_0
reset_out_0
reset_req_1
reset_out_1
tre_reset_req
tre_reset_in tre_reset_req
tre_reset_in
Transceiver Reset Sequencer Inferred Block
clk_usrpin
Optional
user reset
Transceiver Reset Endpoints—The Transceiver PHY IP core contains Transceiver
Reset Endpoints (TREs)
(29)
.
Transceiver Reset Sequencer—The Quartus Prime software detects the presence of
TREs and automatically inserts only one Transceiver Reset Sequencer (TRS)
(29)
. The
tx_analogreset and rx_analogreset requests from the reset controller (User
coded or Transceiver PHY Reset Controller) is received by the TREs. The TRE sends the
reset request to the TRS for scheduling. TRS schedules all the requested PMA resets
and sends them back to TREs. You can use either Transceiver PHY Reset Controller or
your own reset controller. However, for the TRS to work correctly, the required timing
duration must be followed. See Figure 147 on page 246 for required timing duration.
Note: The TRS IP is an inferred block and is not visible in the RTL. You have no control over
this block.
CLKUSR connection—The clock to the TRS must be stable and free-running
(100-125 MHz). By default, the Quartus Prime software automatically connects the
TRS clock input to the CLKUSR pin on the device. If you are using the CLKUSR pin for
your own logic (feeding it to the core), you must instantiate
altera_a10_xcvr_clock_module
altera_a10_xcvr_clock_module reset_clock (.clk_in(mgmt_clk));
For more information about the CLKUSR pin, refer to the Cyclone 10 GX Pin
Connection Guidelines.
(29)
There is only one centralized TRS instantiated for one or more Native PHY.
4. Resetting Transceiver Channels
UG-20070 | 2018.09.24
Intel
®
Cyclone
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English