Intel Cyclone 10 GX User Manual

Protocol Transceiver PHY IP
Core
PCS Support Transceiver
Configuration Rule
Protocol Preset
SATA 3.0/2.0/1.0 and
SAS 2.0/1.1/1.0
Native PHY IP core Standard Basic/Custom
(Standard PCS)
SAS Gen2/Gen1.1/
Gen1
SATA Gen3/Gen2/
Gen1
HiGig/HiGig+/HiGig2/
HiGig2+
Native PHY IP core Standard Basic/Custom
(Standard PCS)
User created
JESD204A / JESD204B Native PHY IP core Standard and
Enhanced
Basic/Custom
(Standard PCS) Basic
(Enhanced PCS)
User created
Custom and other
protocols
Native PHY IP core Standard and
Enhanced
PCS Direct
Basis/Custom
(Standard PCS)
Basic (Enhanced PCS)
Basic/Custom with
Rate Match (Standard
PCS)
PCS Direct
User created
2.4. Using the Cyclone 10 GX Transceiver Native PHY IP Core
This section describes the use of the Intel-provided Cyclone 10 GX Transceiver Native
PHY IP core. This Native PHY IP core provides direct access to Cyclone 10 GX
transceiver PHY features.
Use the Native PHY IP core to configure the transceiver PHY for your protocol
implementation. To instantiate the IP, click Tools ➤ IP Catalog to select your IP core
variation. Use the Parameter Editor to specify the IP parameters and configure the
PHY IP for your protocol implementation. To quickly configure the PHY IP, select a
preset that matches your protocol configuration as a starting point. Presets are PHY IP
configuration settings for various protocols that are stored in the IP Parameter
Editor. Presets are explained in detail in the Presets section below.
You can also configure the PHY IP by selecting an appropriate Transceiver
Configuration Rule. The transceiver configuration rules check the valid combinations
of the PCS and PMA blocks in the transceiver PHY layer, and report errors or warnings
for any invalid settings.
Use the Native PHY IP core to instantiate the following PCS options:
• Standard PCS
• Enhanced PCS
• PCS Direct
Based on the Transceiver Configuration Rule that you select, the PHY IP core selects
the appropriate PCS. The PHY IP core allows you to select all the PCS blocks if you
intend to dynamically reconfigure from one PCS to another. Refer to General and
Datapath Parameters section for more details on how to enable PCS blocks for
dynamic reconfiguration.
After you configure the PHY IP core in the Parameter Editor, click Generate HDL to
generate the IP instance. The top level file generated with the IP instance includes all
the available ports for your configuration. Use these ports to connect the PHY IP core
to the PLL IP core, the reset controller IP core, and to other IP cores in your design.
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Intel
®
Cyclone
®
10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English