Name Bit Functionality Description
[8] Synchronous header error status Active-high status signal that indicates a
synchronous header error.
[9] Block lock is achieved Active-high status signal indicating when block
lock is achieved.
[11:10] Synchronous header The value 2'b01 indicates a data word. The
value 2'b10 indicates a control word.
[17:12] Unused
[18] Synchronous header error status Active-high status signal that indicates a
synchronous header error.
[19] Block lock is achieved Active-high status signal indicating when Block
Lock is achieved.
Table 60. Bit Encodings for Basic Mode
In this case, the total word length is 67-bit with 64-bit data and 2-bit synchronous header.
Name Bit Functionality Description
rx_control
[1:0] Synchronous header The value 2'b01 indicates a data word. The value
2'b10 indicates a control word.
[2] Inversion control A logic low indicates that built-in disparity
generator block in the Enhanced PCS maintains
the running disparity.
2.4.10. Standard PCS Ports
Figure 14. Transceiver Channel using the Standard PCS Ports
Standard PCS ports will appear, if either one of the transceiver configuration modes is selected that uses
Standard PCS or if Data Path Reconfiguration is selected even if the transceiver configuration is not one of
those that uses Standard PCS.
reconfig_reset
reconfig_clk
reconfig_avmm
Parallel Data, Control, Clocks
TX FIFO
8B/10B Encoder/Decoder
Reconfiguration
Registers
TX Standard PCS
RX Standard PCS
Nios Hard
Calibration IP
TX PMA
Serializer
RX PMA
DeserializerCDR
tx_cal_busy
rx_cal_busy
Serial Data
Optional Ports
CDR Control
PCIe
Serial Data
Clock
Generation
Block
tx_serial_clk0
(from TX PLL)
tx_analog_reset
Parallel Data, Control, Clocks
RX FIFO
Rate Match FIFO
Word Aligner & Bitslip
PCIe
rx_analog_reset
Clocks
PRBS
Bit & Byte Reversal
Polarity Inversion
PCIe
Optional Ports
Clocks
Cyclone 10 Transceiver Native PHY
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Intel
®
Cyclone
®
10 GX Transceiver PHY User Guide
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