4. Resetting Transceiver Channels
To ensure that transceiver channels are ready to transmit and receive data, you must
properly reset the transceiver PHY. Intel recommends a reset sequence that ensures
the physical coding sublayer (PCS) and physical medium attachment (PMA) in each
transceiver channel initialize and function correctly. You can either use the Transceiver
PHY Reset Controller or create your own reset controller.
4.1. When Is Reset Required?
You can reset the transmitter (TX) and receiver (RX) data paths independently or
together. The recommended reset sequence requires reset and initialization of the PLL
driving the TX or RX channels, as well as the TX and RX datapaths. A reset is required
after any of the following events:
Table 156. Reset Conditions
Event Reset Requirement
Device power up and
configuration
Requires reset to the transceiver PHY and the associated PLLs to a known initialize state.
PLL reconfiguration Requires reset to ensure that the PLL acquires lock and also to reset the PHY. Both the
PLL and the transmitter channel must be held in reset before performing PLL
reconfiguration.
PLL reference clock frequency
change
Requires reset to the PLL to ensure PLL lock. You must also reset the PHY.
PLL recalibration Requires reset to the PLL to ensure PLL lock. You must also reset the PHY. Both the PLL
and the transmitter channel must be held in reset before performing PLL recalibration.
PLL lock loss or recovery Requires reset after a PLL acquired lock from a momentary loss of lock. You must also
reset the PHY.
Channel dynamic
reconfiguration
Requires holding the channel in reset before performing a dynamic reconfiguration that
causes rate change. A PLL reset is not required during channel reconfiguration.
Optical module connection Requires reset of RX to ensure lock of incoming data.
RX CDR lock mode change Requires reset of the RX channel any time the RX clock and data recovery (CDR) block
switches from lock-to-reference to lock-to-data RX channel.
UG-20070 | 2018.09.24
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