Intel Cyclone 10 GX User Manual

a.
Wait for rx_analogreset_ack to go high, to ensure successful assertion of
rx_analogreset. rx_analogreset_ack goes high when TRS has
successfully completed the reset request for assertion.
b.
Deassert rx_analogreset.
2.
Wait for rx_analogreset_ack to go low, to ensure successful deassertion of
rx_analogreset. rx_analogreset_ack goes low when TRS has successfully
completed the reset request for deassertion.
3.
Ensure rx_is_lockedtodata signal goes high after the CDR is locked to data.
Wait for rx_analogreset_ack to go low before monitoring
rx_is_lockedtodata signal.
4.
Deassert rx_digitalreset after a minimum of t
LTD
(minimum of 4 μs) after
rx_is_lockedtodata goes high.
Figure 160. Dynamic Reconfiguration of Receiver Channel During Device Operation
Device Power Up
rx_cal_busy
rx_analogreset
rx_is_lockedtodata
rx_digitalreset
rx_analogreset_ack
Legal
Reconfiguration
Window
1 2 43
t
LTD
min 4 μs
4.3.3. Transceiver Blocks Affected by Reset and Powerdown Signals
You must reset the digital PCS each time you reset the analog PMA or PLL. However,
you can reset the digital PCS block alone.
Table 158. Transceiver Blocks Affected by Specified Reset and Powerdown Signals
Transceiver
Block
pll_powerdown tx_analogreset tx_digitalreset rx_analogreset rx_digitalreset
CMU PLL Yes
ATX PLL Yes
fPLL Yes
CDR Yes
Receiver
Standard PCS
Yes
Receiver
Enhanced PCS
Yes
continued...
4. Resetting Transceiver Channels
UG-20070 | 2018.09.24
Intel
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Cyclone
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English