Intel Cyclone 10 GX User Manual

Table 139. Dynamic Reconfiguration
Parameter Value
Enable dynamic reconfiguration Off
Share reconfiguration interface Off
Enable Altera Debug Master Endpoint Off
Enable embedded debug Off
Enable capability registers Off
Set user-defined IP identifier 0
Enable control and status registers Off
Enable prbs soft accumulators Off
Configuration file prefix
altera_xcvr_native_c10
Generate SystemVerilog package file Off
Generate C header file Off
Generate MIF (Memory Initialization File) Off
Table 140. Generation Options
Parameter Value
Generate parameter documentation file On
2.9. Other Protocols
2.9.1. Using the "Basic (Enhanced PCS)" Configuration
You can use Cyclone 10 GX transceivers to configure the Enhanced PCS to support
other 10G or 10G-like protocols. The Basic (Enhanced PCS) transceiver configuration
rule allows access to the Enhanced PCS with full user control over the transceiver
interfaces, parameters, and ports.
You can configure the transceivers for Basic functionality using the Native PHY IP
Basic (Enhanced PCS) transceiver configuration rule.
Note: This configuration supports the FIFO in phase compensation and register modes. You
can implement all other required logic for your specific application, such as standard
or proprietary protocol multi-channel alignment in the FPGA fabric in soft IP.
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English