Intel Cyclone 10 GX User Manual

2.7.3. How to Connect TX PLLs for PIPE Gen1 and Gen2 Modes
Figure 63. Use fPLL for Gen1/Gen2 x1 Mode
CDR
CGB
Ch 4
CDR
CGB
Ch 3
CDR
CGB
Ch 2
CDR
CGB
Ch 1
CDR
CGB
Ch 0
CDR
CGB
Ch 5
4
4Master
CGB1
Master
CGB0
6
6
6
6
6
6
X1 Network
ATX PLL1
fPLL1
fPLL0
ATX PLL0
Path for Clocking in
Gen1/Gen2 x1 Mode
Path for Clocking in
Gen1/Gen2 x1 Mode
Notes:
1. The figure shown is just one possible combination for the PCIe Gen1/Gen2 x1 mode.
2. Gen1/Gen2 x1 mode uses the ATX PLL or fPLL.
3. Gen1/Gen2 x1 can use any channel from the given bank for which the ATX PLL or fPLL is enabled.
4. Connect pll_pcie_clk from either ATX PLL or fPLL to the pipe_hclk_in port on Native PHY.
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Intel
®
Cyclone
®
10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English