Intel Cyclone 10 GX User Manual

Figure 61. Rate Match FIFO Empty
The rate match FIFO automatically inserts /K30.7/ (9'h1FE) after the data byte that causes the FIFO to become
empty and drives pipe_rx_status[2:0] = 3'b110 synchronous to the inserted /K30.7/ (9'h1FE). The figure
below shows rate match FIFO empty condition in PIPE mode. The rate match FIFO becomes empty after
reading out data byte D3.
D1 D2 D3 D4 D5 D6
D1 D2 D3 /K.30.7/ D4
D5
tx_parallel_data
rx_parallel_data
pipe_rx_status[2:0] xxx xxx xxx 3’b110 xxx
xxx
PIPE 0 ppm
The PIPE mode also has a "0 ppm" configuration option that can be used in
synchronous systems. The Rate Match FIFO Block is not expected to do any clock
compensation in this configuration, but latency will be minimized.
2.7.2.1.8. PCIe Reverse Parallel Loopback
PCIe reverse parallel loopback is only available in a PCIe functional configuration for
Gen1 and Gen2 data rates. The received serial data passes through the receiver CDR,
deserializer, word aligner, and rate matching FIFO buffer. The data is then looped back
to the transmitter serializer and transmitted out through the transmitter buffer. The
received data is also available to the FPGA fabric through the rx_parallel_data
port. This loopback mode is based on PCIe specification 2.0. Cyclone 10 GX devices
provide an input signal pipe_tx_detectrx_loopback[0:0] to enable this loopback
mode.
Note: This is the only loopback option supported in PIPE configurations.
Figure 62. PCIe Reverse Parallel Loopback Mode Datapath
PCI Express Hard IP
PIPE Interface
RX
FIFO
Byte
Deserializer
8B/10B Decoder
Rate Match FIFO
Receiver PMA
Word Aligner
Deserializer
CDR
Receiver Standard PCS
Transmitter Standard PCS
Transmitter PMA
Serializer
tx_serial_data rx_serial_data
FPGA
Fabric
TX TX
FIFOFIFO
Byte SerializerByte Serializer
8B/10B Encoder8B/10B Encoder
PRBS
Generator
TX Bit Slip
PRBS
Reverse Parallel
Loopback Path
Verifier
Related Information
• Cyclone 10 GX Standard PCS Architecture on page 299
• Intel PHY Interface for the PCI Express (PIPE) Architecture PCI Express 2.0
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English