Intel Cyclone 10 GX User Manual

The MIF file and C header file are set up similarly to the SystemVerilog package file.
Multiple transceiver features may reside at the same address. Also, a single
transceiver feature may span across multiple addresses.
Dynamic reconfiguration requires at least two configurations of the Transceiver Native
PHY IP core or PLL IP core. One configuration defines the base transceiver or PLL
configuration and the other configurations define the modified or target configurations.
Use the IP Parameter Editor to create base and modified configurations of the
Transceiver Native PHY or PLL IP core, according to the following table.
Note: You can generate the base and modified configuration files in the same or different
folders. If you use the same folder, each configuration name must be unique.
Intel recommends following the flow described in the Steps to Perform Dynamic
Reconfiguration section when performing dynamic reconfiguration of either the Native
PHY IP core or transmit PLL IP core.
Related Information
• Steps to Perform Dynamic Reconfiguration on page 328
• Analog Parameter Settings on page 388
6.4. Multiple Reconfiguration Profiles
You can optionally enable multiple configurations or profiles in the same Native PHY IP
and/or ATX PLL IP core Parameter Editors for performing dynamic reconfiguration. This
allows the IP Parameter Editor to create, store, and analyze the parameter settings for
multiple configurations or profiles.
When you enable multiple reconfiguration profiles feature, the Native PHY and/or ATX
PLL IP cores can generate configuration files for all the profiles in the format desired
(SystemVerilog package, MIF, or C header file). The configuration files are located in
the <IP instance name>/reconfig/ subfolder of the IP instance with the
configuration profile index added to the filename. For example, the configuration file
for Profile 0 is stored as <filename_CFG0.sv>. The Quartus Prime Timing Analyzer
includes the necessary timing paths for all the configurations based on initial and
target profiles. You can also generate reduced configuration files that contain only the
attributes that differ between the multiple configured profiles. You can create up to
eight reconfiguration profiles (Profile 0 to Profile 7) at a time for each instance of the
Native PHY/ATX PLL IP core.
You can optionally allow the Native PHY IP core to include PMA Analog settings in the
configuration files by enabling the feature Include PMA Analog settings in
configuration files in the Dynamic Reconfiguration tab of the Transceiver Native
PHY IP Parameter Editor. This feature is disabled by default. Enabling this feature adds
the PMA analog settings specified in the Analog PMA settings (Optional) tab of the
Native PHY IP Parameter Editor to the configuration files. Even with this option
enabled in the Native PHY IP Parameter Editor, you must still specify QSF assignments
for your analog settings when compiling your static design. The analog settings
selected in the Native PHY IP Parameter Editor are used only to include these settings
and their dependent settings in the selected configuration files. Refer to the Analog
Parameter Settings chapter for details about QSF assignments for the analog settings.
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English