Intel Cyclone 10 GX User Manual

Parameters Value
Enable TX polarity inversion On/Off
Enable tx_polinv port On/Off
Enable RX bit reversal Off
Enable rx_std_bitrev_ena port Off
Enable RX byte reversal Off
Enable rx_std_byterev_ena port Off
Enable RX polarity inversion On/Off
Enable rx_polinv port On/Off
Enable rx_std_signaldetect port On/Off
All options under PCIe Ports Off
2.6.2. 10GBASE-R and 10GBASE-R with IEEE 1588v2 Variants
10GBASE-R PHY is the Ethernet-specific physical layer running at a 10.3125-Gbps
data rate as defined in Clause 49 of the IEEE 802.3-2008 specification. Cyclone 10 GX
transceivers can implement 10GBASE-R variants like 10GBASE-R with IEEE 1588v2.
The 10GBASE-R parallel data interface is the 10 Gigabit Media Independent Interface
(XGMII) that interfaces with the Media Access Control (MAC), which has the optional
Reconciliation Sub-layer (RS).
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English