Intel Cyclone 10 GX User Manual

Parameters Value
RX FIFO mode
low latency (for GbE)
register_fifo (for GbE with IEEE 1588v2)
Enable tx_std_pcfifo_full port On/Off
Enable tx_std_pcfifo_empty port On/Off
Enable rx_std_pcfifo_full port On/Off
Enable rx_std_pcfifo_empty port On/Off
TX byte serializer mode Disabled
RX byte deserializer mode Disabled
Enable TX 8B/10B encoder On
Enable TX 8B/10B disparity control On/Off
Enable RX 8B/10B decoder On
RX rate match FIFO mode
gige (for GbE)
disabled (for GbE with IEEE 1588v2)
RX rate match insert / delete -ve pattern (hex)
0x000ab683 (/K28.5/D2.2/) (for GbE)
0x00000000 (disabled for GbE with IEEE
1588v2)
RX rate match insert / delete +ve pattern (hex)
0x000a257c (/K28.5/D16.2/) (for GbE)
0x00000000 (disabled for GbE with IEEE
1588v2)
Enable rx_std_rmfifo_full port
On/Off
(option disabled for GbE with IEEE 1588v2)
Enable rx_std_rmfifo_empty port
On/Off
(option disabled for GbE with IEEE 1588v2)
Enable TX bit slip Off
Enable tx_std_bitslipboundarysel port On/Off
RX word aligner mode Synchronous state machine
RX word aligner pattern length 7
RX word aligner pattern (hex)
0x000000000000007c (Comma) (for 7-bit
aligner pattern length), 0x000000000000017c
(/K28.5/) (for 10-bit aligner pattern length)
Number of word alignment patterns to achieve sync 3
Number of invalid data words to lose sync 3
Number of valid data words to decrement error count 3
Enable fast sync status reporting for deterministic latency SM On/Off
Enable rx_std_wa_patternalign port Off
Enable rx_std_wa_a1a2size port Off
Enable rx_std_bitslipboundarysel port Off
Enable rx_bitslip port Off
Enable TX bit reversal Off
Enable TX byte reversal Off
continued...
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English