Intel Cyclone 10 GX User Manual

Table 86. TX PMA Parameters
Parameter Value
TX channel bonding mode Not bonded
TX local clock division factor 1, 2, 4, 8
Number of TX PLL clock inputs per channel 1, 2, 3, 4
Initial TX PLL clock input selection 0 to 3
Enable tx_pma_clkout port On/Off
Enable tx_pma_div_clkout port On/Off
tx_pma_div_clkout division factor Disabled, 1, 2, 33, 40, 66
Enable tx_pma_elecidle port On/Off
Enable rx_seriallpbken port On/Off
Table 87. RX PMA Parameters
Parameter Value
Number of CDR reference Clocks 1 to 5
Selected CDR reference clock 0 to 4
Selected CDR reference clock frequency
Select legal range defined by the Quartus Prime
software
PPM detector threshold 100, 300, 500, 1000
CTLE adaptation mode manual
Enable rx_pma_clkout port On/Off
Enable rx_pma_div_clkout port On/Off
rx_pma_div_clkout division factor Disabled, 1, 2, 33, 40, 66
Enable rx_pma_iqtxrx_clkout port On/Off
Enable rx_pma_clkslip port On/Off
Enable rx_is_lockedtodata port On/Off
Enable rx_is_lockedtoref port On/Off
Enable rx_set_locktodata and rx_set_locktoref ports On/Off
Enable rx_seriallpbken port On/Off
Enable PRBS verifier control and status ports On/Off
Table 88. Standard PCS Parameters
Parameters Value
Standard PCS / PMA interface width 10
FPGA fabric / Standard TX PCS interface width 8
FPGA fabric / Standard RX PCS interface width 8
Enable Standard PCS low latency mode Off
TX FIFO mode
low latency (for GbE)
register_fifo (for GbE with IEEE 1588v2)
continued...
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English