Intel Cyclone 10 GX User Manual

Figure 42. Connection Guidelines for a GbE/GbE with IEEE 1588v2 PHY Design
reset
Pattern
Generator
Pattern
Checker
PLL
Reset
Controller
Cyclone 10
Transceiver
Native
PHY
tx_parallel_data
tx_datak
tx_clkout
pll_ref_clk
reset
tx_serial_clk
pll_locked
pll_powerdown (2)
rx_ready
tx_ready
clk
reset
tx_digitalreset
tx_analogreset
rx_digitalreset
rx_analogreset
rx_is_lockedtodata
rx_parallel_data
rx_datak
rx_clkout
tx_serial_data
rx_serial_data
tx_cal_busy
rx_cal_busy
Note:
1. The pll_cal_busy signal is not available when using the CMU PLL.
2. The pll_powerdown signal is not available separately for user control when using the fPLL.
The reset controller handles PLL reset for the fPLL.
pll_cal_busy (1)
rx_cdr_refclk
8. Simulate your design to verify its functionality.
2.6.1.6. Native PHY IP Parameter Settings for GbE and GbE with IEEE 1588v2
This section contains the recommended parameter values for this protocol. Refer to
Using the Cyclone 10 GX Transceiver Native PHY IP Core for the full range of
parameter values.
Table 85. General and Datapath Options
The first two sections of the Native PHY [IP] parameter editor for the Native PHY IP provide a list of general
and datapath options to customize the transceiver.
Parameter
Value
Message level for rule violations
error
warning
Transceiver configuration rules
GbE (for GbE)
GbE 1588 (for GbE with IEEE 1588v2)
Transceiver mode
TX/RX Duplex
TX Simplex
RX Simplex
Number of data channels 1 to 12
Data rate
1250 Mbps
Enable datapath and interface reconfiguration On/Off
Enable simplified data interface On/Off
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English