Intel Cyclone 10 GX User Manual

2.9.1.6. TX Data Polarity Inversion
Use the TX data polarity inversion feature to swap the positive and negative signals of
a serial differential link if they were erroneously swapped during board layout. To
enable TX data polarity inversion, select the Enable TX data polarity inversion
option in the Gearbox section of Platform Designer. It can also be dynamically
controlled with dynamic reconfiguration.
2.9.1.7. RX Data Bitslip
The RX data bit slip in the RX gearbox allows you to slip the recovered data. An
asynchronous active high edge on the rx_bitslip port changes the word boundary,
shifting rx_parallel_data one bit at a time. Use the rx_bitslip port with its own
word aligning logic. Assert the rx_bitslip signal for at least two parallel clock cycles
to allow synchronization. You can verify the word alignment by monitoring
rx_parallel_data. Using the RX data bit slip feature is optional.
Figure 82. RX Bit Slip
rx_clkout
rx_bitslip
rx_parallel_data[63:0]
64’d164’d0
2.9.1.8. RX Data Polarity Inversion
Use the RX data polarity inversion feature to swap the positive and negative signals of
a serial differential link if they were erroneously swapped during board layout. To
enable RX data polarity inversion, select the Enable RX data polarity inversion
option in the Gearbox section of Platform Designer. It can also be dynamically
controlled with dynamic reconfiguration.
2.9.2. Using the Basic/Custom, Basic/Custom with Rate Match
Configurations of Standard PCS
Use one of the following transceiver configuration rules to implement protocols such as
SONET/SDH, SDI/HD, SATA, or your own custom protocol:
• Basic protocol
• Basic protocol with low latency enabled
• Basic with rate match protocol
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English