Intel Cyclone 10 GX User Manual

Parameter Gen1 PIPE Gen2 PIPE
Configuration Files
Configuration file prefix N/A N/A
Generate SystemVerilog package file N/A N/A
Generate C Header file N/A N/A
Generate MIF (Memory Initialize file) N/A N/A
Generation Options
Generate parameter documentation file Enable Enable
Related Information
Using the Cyclone 10 GX Transceiver Native PHY IP Core on page 26
2.7.7. ATX PLL IP Parameter Core Settings for PIPE
Table 125. Parameters for Cyclone 10 GX ATX PLL IP core in PIPE Gen1, Gen2 modes
This section contains the recommended parameter values for this protocol. Refer to Using the Cyclone 10 GX
Transceiver Native PHY IP Core for the full range of parameter values.
Parameter Gen1 PIPE Gen2 PIPE
PLL
General
Message level for rule violations Error Error
Protocol Mode PCIe Gen 1 PCIe Gen 2
Bandwidth Low, medium, high Low, medium, high
Number of PLL reference clocks 1 1
Selected reference clock source 0 0
Ports
Primary PLL clock output buffer GX clock output buffer GX clock output buffer
Enable PLL GX clock output port Enable Enable
Enable PCIe clock output port pll_pcie_clk Enable Enable
Enable ATX to fPLL cascade clock output port Disable Disable
Output Frequency
PLL output frequency 1250MHz 2500MHz
PLL output datarate 2500Mbps 5000Mbps
Enable fractional mode Disable Disable
PLL integer reference clock frequency 100MHz, 125MHZ 100MHz, 125MHZ
Configure counters manually Disable Disable
Multiple factor (M counter) N/A N/A
Divide factor (N counter) N/A N/A
Divide factor (L counter) N/A N/A
continued...
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English