Intel Cyclone 10 GX User Manual

Parameter Gen1 PIPE Gen2 PIPE
Master Clock Generation Block
MCGB
Include master clock generation block Disable for x1
Enable for x2, x4
Disable for x1
Enable for x2, x4
Clock division factor N/A for x1
1 for x2, x4
N/A for x1
1 for x2, x4
Enable x6/xN non-bnded high speed clock output port N/A for x1
Disable for x2, x4
N/A for x1
Disable for x2, x4
Enable PCIe clock switch interface N/A for x1
Disable for x2, x4
N/A for x1
Enable for x2, x4
Number of auxiliary MCGB clock input ports N/A for x1
0 for x2, x4
N/A for x1
0 for x2, x4
MCGB input clock frequency 1250 MHz 2500 MHz
MCGB output data rate 2500 Mbps 5000 Mbps
Bonding
Enable bonding clock output ports N/A for x1
Enable for x2, x4
N/A for x1
Enable for x2, x4
Enable feedback compensation bonding N/A for x1 design
Disable for x2, x4
N/A for x1 design
Disable for x2, x4
PMA interface width N/A for x1 design
10 for x2, x4
N/A for x1 design
10 for x2, x4
Dynamic Reconfiguration
Enable dynamic reconfiguration Disable Disable
Enable Altera Debug Master Endpoint Disable Disable
Separate avmm_busy from reconfig_waitrequest N/A N/A
Optional Reconfiguration Logic
Enable capability registers N/A N/A
Set user-defined IP identifier N/A N/A
Enable control and status registers N/A N/A
Configuration Files
Configuration file prefix N/A N/A
Generate SystemVerilog package file N/A N/A
Generate C Header file N/A N/A
Generate MIF (Memory Initialize file) N/A N/A
Generation Options
Generate parameter documentation file Enable Enable
Related Information
Using the Cyclone 10 GX Transceiver Native PHY IP Core on page 26
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English