Intel Cyclone 10 GX User Manual

As indicated in the figures above, the fitter picks either physical CH1 or CH4 as the
PCS master in bonded configurations for PIPE.
2.8. CPRI
The common public radio interface (CPRI) is a high-speed serial interface developed
for wireless network radio equipment controller (REC) to uplink and downlink data
from available remote radio equipment (RE).
The CPRI protocol defines the interface of radio base stations between the REC and
the RE. The physical layer supports both the electrical interfaces (for example,
traditional radio base stations) and the optical interface (for example, radio base
stations with a remote radio head). The scope of the CPRI specification is restricted to
the link interface only, which is a point-to-point interface. The link has all the features
necessary to enable a simple and robust usage of any given REC and RE network
topology, including a direct interconnection of multiport REs.
2.8.1. Transceiver Channel Datapath and Clocking for CPRI
Figure 70. Transceiver Channel Datapath and Clocking for CPRI
RX
FIFO
Byte
Deserializer
8B/10B Decoder
Rate Match FIFO
Receiver PMA
Word Aligner
Deserializer
CDR
Receiver Standard PCS
Transmitter Standard PCS
Transmitter PMA
Serializer
tx_serial_data
rx_serial_data
FPGA
Fabric
TX
FIFO
Byte Serializer
8B/10B Encoder
PRBS
Generator
TX Bit Slip
/2, /4
/2, /4
Parallel Clock
Serial Clock
Parallel and Serial Clock
Parallel and Serial Clock
Clock Divider
rx_pma_div_clkout
Serial Clock
Clock Generation Block (CGB)
ATX PLL
CMU PLL
fPLL
tx_coreclkin
rx_coreclkin
rx_clkout or
tx_clkout
Parallel Clock
(Recovered)
Parallel Clock
(From Clock
Divider)
tx_clkout
tx_clkout
tx_clkout
rx_clkout
PRBS
Verifier
tx_pma_div_clkout
20
20
153.6 MHz
153.6 MHz
32
32
153.6 MHz
153.6 MHz
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
149

Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English